參數(shù)資料
型號: T8502
元件分類: Codec
英文描述: T8502 and T8503 Dual PCM Codecs with Filters
中文描述: T8502和T8503雙的PCM編解碼器與濾波器
文件頁數(shù): 4/16頁
文件大小: 440K
代理商: T8502
4
Lucent Technologies Inc.
Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid
exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics
Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and
protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the
model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500
,
capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD
threshold presented here was obtained by using these circuit parameters:
Electrical Characteristics
Specifications apply for T
A
= –40
°
C to +85
°
C, V
DD
= 5 V
±
5%, MCLK = either 2.048 MHz or 4.096 MHz, and
GND = 0 V, unless otherwise noted.
dc Characteristics
Table 2. Digital Interface
Parameter
Symbol
T
stg
V
DD
P
D
Min
–55
–0.5
Max
150
6.5
Unit
°
C
V
V
mW
Storage Temperature Range
Power Supply Voltage
Voltage on Any Pin with Respect to Ground
Maximum Power Dissipation (package limit)
0.5 + V
DD
600
HBM ESD Threshold Voltage
Device
T8502
T8503
Rating
>2000
>2000
Parameter
Symbol
V
IL
V
IH
V
OL
V
OH
Test Conditions
All digital inputs
All digital inputs
D
X
, I
L
= 3.2 mA
D
X
, I
L
= –3.2 mA
D
X
, I
L
= –320
μ
A
GNDD < V
IN
< V
DD
GNDD < V
IN
< V
DD
GNDD < V
IN
< V
DD
D
X
Min
2.0
2.4
3.5
–10
2
–120
–30
Typ
<
±
2
Max
0.8
0.4
10
150
–2
30
5
Unit
V
V
V
V
V
μ
A
μ
A
μ
A
μ
A
pF
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Current, Pins 9, 12
Input Current, Pins 7, 8, 13, 14, 15
Input Current, Pins 5, 16
Output Current in High-impedance State
Input Capacitance
I
I
I
I
I
I
I
OZ
C
I
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