參數(shù)資料
型號(hào)： T8503
元件分類： Codec
英文描述： T8502 and T8503 Dual PCM Codecs with Filters
中文描述： T8502和T8503雙的PCM編解碼器與濾波器
文件頁(yè)數(shù)： 1/16頁(yè)
文件大小： 440K
代理商： T8503
Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Features
I
+5 V only
I
Two independent channels
I
Pin-selectable receive gain control
I
Pin-selectable
μ
-law or A-law companding
I
Automatic powerdown mode
I
Low-power, latch-up-free CMOS technology
— 40 mW/channel typical operating power
dissipation
— 12.5 mW/channel typical standby power
dissipation
I
Automatic master clock frequency selection
— 2.048 MHz or 4.096 MHz
I
Independent transmit and receive frame strobes
I
2.048 MHz or 4.096 MHz data rate
I
On-chip sample and hold, autozero, and precision
voltage reference
I
Differential architecture for high noise immunity
and power supply rejection
I
Meets or exceeds ITU-T G.711—G.714 require-
ments and VF characteristics of D3/D4 (as per
Bellcore PUB43801)
I
Operating temperature range: –40
°
C to +85
°
C
Description
The T8502 and T8503 devices are single-chip, two-
channel,
μ
-law/A-law PCM codecs with filters. These
integrated circuits provide analog-to-digital and
digital-to-analog conversion. They provide the
transmit and receive filtering necessary to interface a
voice telephone circuit to a time-division multiplexed
system. These devices are packaged in both 20-pin
SOJs and 20-pin SOGs.
The T8502 differs from the T8503 in its timing mode.
The T8502 operates in the delayed timing mode
(digital data is valid one clock cycle after frame sync
goes high), and the T8503 operates in the
nondelayed timing mode (digital data valid when
frame sync goes high) (see Figures 5 and 6).
5-3579.b
Figure 1. Block Diagram
FS
X
0
FS
R
0
FS
X
1
FS
R
1
GNDD
GS
X
0
VF
X
IN0
VF
R
O0
GS
X
1
VF
X
IN1
VF
R
O1
–
+
FILTER
NETWORK
ENCODER
CHANNEL 0
+2.4 V
DECODER
PCM
INTERFACE
GAIN
CONTROL
INTERNAL TIMING
& CONTROL
BIAS
CIRCUITRY
&
REFERENCE
CHANNEL 1
FILTER
NETWORK
D
X
D
R
MCLK
ASEL
V
DD
GNDA (2)
GS0
GS1
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相關(guān)代理商/技術(shù)參數(shù)
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