參數(shù)資料
型號(hào): T8503
元件分類: Codec
英文描述: T8502 and T8503 Dual PCM Codecs with Filters
中文描述: T8502和T8503雙的PCM編解碼器與濾波器
文件頁數(shù): 3/16頁
文件大?。?/td> 440K
代理商: T8503
Lucent Technologies Inc.
3
Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Pin Information
(continued)
* I
d
indicates
a pull-down device is included on this lead. I
u
indicates a pull-up device is included on this lead.
Table 1. Pin Descriptions
Symbol
VF
X
IN1
VF
X
IN0
Pin
20
1
Type
*
I
Name/Function
Voice Frequency Transmitter Input.
Analog inverting input to the uncommitted oper-
ational amplifier at the transmit filter input. Connect the signal to be digitized to this pin
through a resistor R
I
(see Figure 2).
Gain Set for Transmitter.
Output of the transmit uncommitted operational amplifier.
The pin is the input to the transmit differential filters. Connect the pin to its
corresponding VF
X
IN through a resistor R
F
(see Figure 2).
Voice Frequency Receiver Output.
This pin can drive 2000
(or greater) loads.
GS
X
1
GS
X
0
19
2
O
VF
R
O1
VF
R
O0
V
DD
17
4
6
O
+5 V Power Supply
. This pin should be bypassed to ground with at least 0.1
μ
F of
capacitance as close to the device as possible.
Analog Grounds
. All ground pins must be connected on the circuit board.
GNDA1
GNDA0
D
R
18
3
12
I
Receive PCM Data Input
. The data on this pin is shifted into the device on the falling
edges of MCLK. Data is only entered for valid time slots as defined by the FS
R
inputs.
Transmit PCM Data Output
. This pin remains in the high-impedance state except
during active transmit time slots. An active transmit time slot is defined as one in which
a pulse is present on one of the FS
X
inputs. Data is shifted out on the rising edge of
MCLK.
Master Clock Input
. The frequency must be 2.048 MHz or 4.096 MHz. This clock
serves as the bit clock for all PCM data transfer.
Digital Ground
. Ground connection for the digital circuitry. All ground pins must be
connected on the circuit board.
Transmit Frame Sync
. This signal is an edge trigger and must be high for a minimum
of one MCLK cycle. This signal must be derived from MCLK. The division ratio is 1:256
or 1:512 (FS
X
:MCLK). Each FS
X
input must have a pulse present at the start of the
desired active output time slot. Pulses on FS
X
inputs must be separated by one or more
integer multiples of time slots. If the device is to be used as an A/D converter only, FS
X
must be tied to FS
R
. An internal pull-down device is included on each FS
X
.
Receive Frame Sync
. This signal is an edge trigger and must be high for a minimum
of one MCLK cycle. This signal must be derived from MCLK. The division ratio is 1:256
or 1:512 (FS
R
:MCLK). Each FS
R
input must have a pulse present at the start of the
desired active input time slot. Pulses on FS
R
inputs must be separated by one or more
integer multiples of time slots. If the device is to be used as a D/A converter only, FS
R
must be tied to FS
X
. An internal pull-down device is included on each FS
R
.
Gain Selection
. A high or floating state sets the receive path gain at 0 dB; a logic low
sets the gain to –3.5 dB. A pull-up device is included.
A-Law/
μ
-Law Select
. A logic low selects
μ
-law coding. A logic high selects A-law
coding. A pull-down device is included.
D
X
11
O
MCLK
9
I
GNDD
10
FS
X
1
FS
X
0
13
8
I
d
FS
R
1
FS
R
0
14
7
I
d
GS1
GS0
ASEL
16
5
15
I
u
I
d
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