參數(shù)資料
型號(hào)： T8535B
元件分類(lèi)： Codec
英文描述： T8535B/T8536B Quad Programmable Codec
中文描述： T8535B/T8536B四可編程編解碼器
文件頁(yè)數(shù)： 41/50頁(yè)
文件大?。?/td> 929K
代理商： T8535B
Agere Systems Inc.
41
Preliminary Data Sheet
September 2001
T8535B/T8536B Quad Programmable Codec
Software Interface
(continued)
The following table shows the control bit assignments in the memory control addresses. In all control bit cases, the
bit being set places the function into the active mode as defined in the function column.
Table 21. Control Bit Definition
Control Name
(Address, Decimal)
[Address, Hex]
HBALTAPS
(0—27, 64—91)
[0x00—0x1b,
0x40—0x5b]
RESCTRL
(128)
[0x80]
Bit
Assignment(s)
Function
448
Balance impedance coefficients. Default value is 0x00 for all bytes except
for addresses 3 and 5, which are 0x80, and address 69, which is 0x88.
2—7
1
0
Not used, load as zeros.
A one resets all other internal states. Control addresses are not reset.
A one resets all control addresses to default values. Note that setting this
bit will result in it and all others of this word becoming cleared on the next
PCM frame as a normal part of the reset functionality. Alternatively, hard-
ware reset can be used to reset all control and state functions. It is neces-
sary to wait at least 256
μ
s after asserting this bit before initiating any
other serial I/O transactions.
Load as zeros.
Active/standby mode. A zero causes the channel to enter standby (low-
power) mode and disables the PCM interface for this channel. A one acti-
vates the channel and the corresponding PCM bus interface. Default is
zero.
Receive direction bit offset for the FS signal. Defaults to zero. These
3 bits can be thought of as the least significant bits (RXOFF contains the
more significant bits) of a bit counter that determines the location of the
first bit of the PCM data from FS.
Load as zeros.
Receive time-slot assignment. Defaults to (16 * channel number). Each
time slot represents 8 bits; allow for two time slots when using linear
mode or double-clock mode.
Gain adjustment for gain transfer stage in receive direction. Defaults to
0x0400 (0 dB). This is an 11-bit multiply operation with a maximum gain of
two (6 dB). 0 dB is the maximum recommended setting.
Gain adjustment for tweak gain stage in receive direction. Defaults to
0x01ac (
7.58 dB). This is an 11-bit multiply operation with a maximum
gain of two (6 dB). 0 dB is the maximum recommended setting.
Coefficients for the CTZ termination bleed. Defaults to 0x07ed0000.
CHACTIVE
(129)
[0x81]
1—7
0
RXBITOFF
(130)
[0x82]
5—7
0—4
0—7
RXOFF
(131)
[0x83]
GRX1
(132—133)
[0x84—0x85]
GRX2
(134—135)
[0x86—0x87]
CTZCTRL
(140—143)
[0x8c—0x8f]
0—10
0—10
0—30
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