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參數(shù)資料
| 型號： | T8535B |
| 元件分類： | Codec |
| 英文描述： | T8535B/T8536B Quad Programmable Codec |
| 中文描述： | T8535B/T8536B四可編程編解碼器 |
| 文件頁數(shù)： | 8/50頁 |
| 文件大小： | 929K |
| 代理商： | T8535B |
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8
Agere Systems Inc.
Preliminary Data Sheet
September 2001
T8535B/T8536B Quad Programmable Codec
Pin Information
(continued)
Table 4. Pin Assignments, 68-Pin PLCC, Common Functions
Pin
1
2
3
4
Name
DO
DI
DCLK
CS
Type
O
I
I
I
Name/Description
Serial Data Output.
This is a 3-state output.
Serial Data Input.
Serial Data Clock Input.
Chip Select Input.
This lead determines the interval that the serial interface is
active.
Serial Interface Select.
Leaving this lead open places the serial interface in the nor-
mal mode; grounding it places the interface into the byte-by-byte mode. This lead
has an internal pull-up.
Frequency Synthesizer Power (5 V).
This pin must be tied to V
DD
.
Internal Test Point.
Do not connect to this lead.
Internal Test Point.
Do not connect to this lead.
Synthesizer
Test Point.
Do not connect to this lead.
Synthesizer Ground.
Connect to digital ground. A common AGND, DGND, SGND
plane is highly recommended.
Digital Ground.
Logic ground and return for logic power supply. A common AGND,
DGND, SGND plane is highly recommended.
Digital Power Supply (5 V).
5
INTS
I
10
11
12
13
14
FILTV
PVCOIN
PVCO
PLLT
SGND
PWR
—
—
—
GND
24, 45,
58, 68
28, 40,
55, 66
56
DGND
GND
V
DD
PWR
FS
I
PCM Frame Strobe Input.
This 8 kHz clock must be derived from the same source
as BCLK.
PCM Bit Clock Input.
This lead is used to develop internal clocks for certain clock
rates.
PCM Transmit Data Output.
This is a 3-state output.
PCM Receive Data Input.
Power-On Reset.
A low causes a reset of the entire chip. This pin may be con-
nected to DGND with a 0.1
μ
F capacitor for a power-on reset function, or it may be
driven by external logic. This lead has an internal pull-up.
No Connect.
This pin may be used as a tie point.
57
BCLK
I
59
60
65
DX
DR
RST
O
I
I
67
NC
—
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