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參數(shù)資料
| 型號： | T8538B |
| 元件分類： | Codec |
| 英文描述： | T8538B Quad Programmable Codec |
| 中文描述： | T8538B四可編程編解碼器 |
| 文件頁數(shù)： | 4/44頁 |
| 文件大?。?/td> | 847K |
| 代理商： | T8538B |
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4
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
General Description
(continued)
The PCM bus interface is flexible in that it allows, inde-
pendently, the transmit and receive data for any chan-
nel to be placed in any time slot. The bus can be
operated at a maximum 16.384 Mbits/s rate to accom-
modate a maximum 256 time slots. Separate pins
are provided for each direction of transmission to
allow 4-wire bus operation. The frame strobe signal is
an 8 kHz signal that defines the beginning of the frame
structure for all four channels. The interface will count
8 bits per time slot and insert or read the data for each
channel as programmed. Lower speeds of the PCM
bus are allowed. The PCM clock must be synchronous
with the frame strobe signal.
The microprocessor control interface is a serial inter-
face that uses the classical chip select type of opera-
tion. The interface controls the device by writing or
reading various internal addresses. The command set
consists of simple read and write operations, with the
address determining the effect. All the memory loca-
tions, including the per-chip functions, are organized by
channel.
There are several test modes included to facilitate con-
firmation of correct operation. In the signal path, two
analog and three digital loopback tests are available,
while in the microprocessor interface, there is a write/
read test mode that tests the operation of the memory.
Use of external test access switches allows a complete
test of the signal path through the line card so that cor-
rect operation of various operational modes can be ver-
ified.
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