
8
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Pin Information
(continued)
Table 4. Pin Assignments 64-Pin TQFP, Common Functions
Pin
Name
V
DD
DGND
Type
PWR
GND
Name/Description
1, 15, 27, 41, 55
2, 11, 32, 44, 56
Digital Power Supply (3.3 V).
Digital Ground.
Logic ground and return for logic power supply. A common
AGND, DGND plane is highly recommended.
PCM Frame Strobe Input.
This 8 kHz clock must be derived from the same
source as BCLK.
PCM Bit Clock Input.
This lead is used to develop internal clocks for cer-
tain clock rates.
PCM Transmit Data Output 0.
This is a 3-state output.
PCM Receive Data Input 0.
Backplane Line Driver Enable 0 (Active-Low).
Normally, these open-
drain outputs are floating in a high-impedance state. When a time slot is
active on DX0, this output pulls low to enable a backplane line driver.
PCM Transmit Data Output 1.
This a 3-state output.
PCM Receive Data Input 1.
Backplane Line Driver Enable 1 (Active-Low).
Normally, these open-
drain outputs are floating in a high-impedance state. When a time slot is
active on DX1, this output pulls low to enable a backplane line driver.
Power-On Reset.
A low causes a reset of the entire chip. This pin may be
connected to DGND with a 0.1
μ
F capacitor for a power-on reset function, or
it may be driven by external logic. This lead has an internal pull-up.
Serial Data Output.
This is a 3-state output.
Serial Data Input.
Serial Data Clock Input.
Chip Select Input.
This lead determines the interval that the serial interface
is active.
Serial Interface Select.
Leaving this lead open places the serial interface in
the normal mode; grounding it places the interface into the byte-by-byte
mode. This lead has an internal pull-up.
42
FS
I
43
BCLK
I
45
46
47
DX0
DR0
TSX0
O
I
O
48
49
50
DX1
DR1
TSX1
O
I
O
54
RST
I
57
58
59
60
DO
DI
DCLK
CS
O
I
I
I
61
INTS
I