參數(shù)資料
型號： T89C51CC01UA-SLSIM
廠商： Atmel
文件頁數(shù)： 118/123頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 32K 44PLCC
標(biāo)準(zhǔn)包裝： 27
系列： AT89C CAN
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： CAN，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 2K x 8
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
配用： AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱： T89C51CC01UASLSIM
PIC18F2XK20/4XK20
DS41303G-page 94
2010 Microchip Technology Inc.
6.4
Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory
be bulk erased. Word erase in the Flash array is not
supported.
When initiating an erase sequence from the Microcon-
troller itself, a block of 64 bytes of program memory is
erased.
The
Most
Significant
16
bits
of
the
TBLPTR<21:6> point to the block being erased. The
TBLPTR<5:0> bits are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash pro-
gram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
The write initiate sequence for EECON2, shown as
steps 4 through 6 in Section 6.4.1 “Flash Program
Memory Erase Sequence”, is used to guard against
accidental writes. This is sometimes referred to as a
long write.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted during the long write
cycle. The long write is terminated by the internal pro-
gramming timer.
6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory is:
1.
Load Table Pointer register with address of
block being erased.
2.
Set the EECON1 register for the erase operation:
set EEPGD bit to point to program memory;
clear the CFGS bit to access program memory;
set WREN bit to enable writes;
set FREE bit to enable the erase.
3.
Disable interrupts.
4.
Write 55h to EECON2.
5.
Write 0AAh to EECON2.
6.
Set the WR bit. This will begin the block erase
cycle.
7.
The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8.
Re-enable interrupts.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY BLOCK
MOVLW
CODE_ADDR_UPPER
; load TBLPTR with the base
MOVWF
TBLPTRU
; address of the memory block
MOVLW
CODE_ADDR_HIGH
MOVWF
TBLPTRH
MOVLW
CODE_ADDR_LOW
MOVWF
TBLPTRL
ERASE_BLOCK
BSF
EECON1, EEPGD
; point to Flash program memory
BCF
EECON1, CFGS
; access Flash program memory
BSF
EECON1, WREN
; enable write to memory
BSF
EECON1, FREE
; enable block Erase operation
BCF
INTCON, GIE
; disable interrupts
Required
MOVLW
55h
Sequence
MOVWF
EECON2
; write 55h
MOVLW
0AAh
MOVWF
EECON2
; write 0AAh
BSF
EECON1, WR
; start erase (CPU stall)
BSF
INTCON, GIE
; re-enable interrupts
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