參數(shù)資料
型號(hào): T89C51RD2-SLSIL
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 0 to 40 MHz Flash Programmable 8-bit Microcontroller
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 10/104頁
文件大?。?/td> 798K
代理商: T89C51RD2-SLSIL
10
T89C51RD2
4243G
8051
05/03
Enhanced Features
In comparison to the original 80C52, the T89C51RD2 implements some new features,
which are
:
The X2 option
The Dual Data Pointer
The extended RAM
The Programmable Counter Array (PCA)
The Watchdog
The 4 level interrupt priority system
The power-off flag
The ONCE mode
The ALE disabling
Some enhanced features are also located in the UART and the Timer 2
X2 Feature and Clock
Generation
The T89C51RD2 core needs only 6 clock periods per machine cycle. This feature called
X2
provides the following advantages:
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Save power consumption while keeping same CPU power (oscillator power saving).
Save power consumption by dividing dynamically operating frequency by 2 in
operating and idle modes.
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
Description
The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1
input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 1 shows the clock generation block diagram. X2 bit is
validated on XTAL1
÷
2 rising edge to avoid glitches when switching from X2 to STD
mode. Figure 2 shows the mode switching waveforms.
Figure 1.
Clock Generation Diagram
XTAL1
2
CKCON reg
X2
State Machine: 6 clock cycles.
CPU control.
F
OSC
F
XTAL
0
1
XTAL1:2
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