參數(shù)資料
型號(hào): T89C51RD2-SLSIL
廠商: TEMIC SEMICONDUCTORS
元件分類(lèi): 微控制器/微處理器
英文描述: 0 to 40 MHz Flash Programmable 8-bit Microcontroller
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 78/104頁(yè)
文件大?。?/td> 798K
代理商: T89C51RD2-SLSIL
78
T89C51RD2
4243G
8051
05/03
Programming Algorithm
To program the T89C51RD2 the following sequence must be exercised:
Check the signature bytes
Check the HSB (VSB mode)
If the security bits are activated, the following commands must be done before
programming:
Unlock test modes (PEULCK mode, pulse 55h and AAh)
Chip erase (CERR mode)
Write FFh in the HSB (PGMS mode)
Write the signature bytes content in the XAF
As the boot loader and the XAF content is lost after a "chip erase", it must be
reprogrammed if needed.
Disable programming access (PELCK mode)
To write a page in the Flash memory, execute the following steps:
Step 0: Enable programming access (PEULCK mode)
Step 1: Activate the combination of control signals (PGML mode)
Step 2: Input the valid address on the address lines (High order bits of the address
must be stable during the complete ALE low time)
Step 3: Activate the combination of control signals (PGML mode)
Step 4: Input the appropriate data on the data lines.
Step 5: Pulse ALE/PROG once.
Repeat step 2 through 5 changing the address and data for end of a 128 bytes page
Step 6: Enable programming access (PEULCK mode)
Step 7: Activate the combination of control signals (PGMC mode)
Step 8: Input the valid address on the address lines.
Step 9: Pulse ALE/PROG once the specified write time is reached.
Repeat step 0 through 9 changing the address and data until the entire array or until the
end of the object file is reached (See Figure 32.)
Step 10: Disable programming access (PELCK mode)
Verify Algorithm
Verify must be done after each byte or block of bytes is programmed. In either case, a
complete verify of the programmed array will ensure reliable programming of the
T89C51RD2.
P 2.7 is used to enable data output.
To verify the T89C51RD2 code the following sequence must be exercised:
Step 1:Activate the combination of program and control signals (PGMV)
Step 2: Input the valid address on the address lines.
Step 3: Read data on the data lines.
Repeat step 2 through 3 changing the address for the entire array verification
(See Figure 32.).
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