參數(shù)資料
型號： TA1383AFG
廠商： Toshiba Corporation
元件分類： 通用總線功能
英文描述： NTSC Chroma Decoder, Multi-Point Scan Sync Processor, H/V Frequency Counter IC for Color TV
中文描述： NTSC制式色度解碼器，多點(diǎn)掃描同步處理器，水平/垂直頻率計(jì)數(shù)器集成電路彩色電視
文件頁數(shù)： 10/47頁
文件大?。?/td> 1010K
代理商： TA1383AFG
TA1383AFG
2005-09-05
10
Signal
Function
Power-On Initial Value
525I-SEP
Switches 525I SEP Mode
Switches H-SEP Mode. (Countermeasure ghost signal)
0: ON
Automatically controls that H-SEP level does not go higher than V-SEP
level, the initial value is 40%.
1: OFF
(1)
OFF
MATRIX SW
Switches matrix.
Sets I/O signal format for input pins (28, 29, and 30) and output pins (22, 23,
and 24).
00: MODE-1 (YC1/YC2
→
YCbCr, Y3/CbCr
→
YCbCr, RGB
→
YCbCr)
01: MODE-2 (YC1/YC2
→
YCbCr, Y3/PbPr
→
YCbCr, RGB
→
YCbCr)
10: MODE-3 (YC1/YC2
→
YPbPr, Y3/CbCr
→
YPbPr, RGB
→
YPbPr)
11: MODE-4 (YC1/YC2
→
YPbPr, Y3/PbPr
→
YPbPr, RGB
→
YPbPr)
Note: Set this function together with INPUT SW, H/V FREQUENCY for each
input signal.
(00)
BANDWIDTH
Switches bandwidth limiting filter (ADC pre-filter).
Sets bandwidth of bandwidth limiting filter and image mute.
00: OFF (through)
01: Filter 1 (Y: 10.3 MHz/
3dB, Cb/Cr: 4.2 MHz/
3dB)
10: Filter 2 (Y: 14.6 MHz/
3dB, Cb/Cr: 6.5 MHz/
3dB)
11: Image mute (Y:
20IRE, CbCr: 0IRE)
OFF
(00)
V-MODE
Switches vertical sync playback mode.
Switches VD OUT (pin 15) sync playback mode.
0: PLL Mode for standard signals 1: Direct Sync Mode
Note 1: Setting 0 is valid only for standard signals. For other signals, set to Direct
Sync Mode.
In PLL Mode for standard signals, VD output starts with 4-
μ
s delay in
relation to V-SYNC.
For other signals, 0.25-H delay.
Note 2: Set this register to (1) except inputting the NTSC and 525I composite
sync format.
PLL for standard
signals
(0)
TEST
Shipment Test Mode. When TEST
=
01 and H/V FREQ
=
111, V-pull-in range is
expanded (Refer to H/V FREQ function explanation). In other case, set to 00.
(00)
GAIN SW
Switches output gain.
Sets output amp gain for pins 22, 23, and 24.
0:
+
6dB 1: 0dB
0dB
(1)
HD-POL
Switches HD output polarity.
Sets HD OUT (pin 17) polarity.
0: Positive polarity 1: Negative polarity
Positive polarity
(0)
VD-POL
Switches VD output polarity.
Sets VD OUT (pin 15) polarity.
0: Positive polarity 1: Negative polarity
Positive polarity
(0)
C-TRAP
Switches chroma trap.
Switches chroma trap for image signals input to pins 2 and 4.
0: OFF 1: ON
OFF
(0)
HD POSI
Adjusts HD output phase.
Sets output phase of HD OUT (pin 17).
0000: 800 ns (2.7% of H cycle) ahead of sync center
1111: Sync center
Note: Sync center is based on 33.75 kHz/3-level sync.
(0000)
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