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參數(shù)資料
| 型號(hào)： | TAS3103DBTR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| 封裝： | GREEN, PLASTIC, TSSOP-38 |
| 文件頁(yè)數(shù)： | 88/148頁(yè) |
| 文件大?。?/td> | 1247K |
| 代理商： | TAS3103DBTR |
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Table 21 lists all viable clock selections for a given audio sample rate (LRCLK). The table only includes those clock
choices that allow enough processing throughput to accomplish all tasks within a given sample time (Ts = 1/LRCLK).
For each entry in the table, the DAP processing time is given in terms of whether the time is greater than 0.5 Ts
(resulting in an input to output delay of 2.5 Ts ), or less than 0.5 Ts (resulting in an input to output delay of 1.5 Ts ).
Table 21 is valid for both master and slave I2S modes (bit IMS at subaddress 0xF9 determines I2S master/slave
selection—see the DPLL and Clock Management section that follows). For all applications, MCLK must be
≥128
LRCLK (FS). In the I2S master mode, MCLK, SCLK (I2S bit clock) LRCLK are all harmonically related. Furthermore,
in the I2S master mode, if a master clock value given in Table 21 is used, the latency realized in performing I2S format
conversions, 1.5 samples or 2.5 samples, is stable and fixed over the duration of operation. However, greater care
must be taken for the I2S slave mode. In this mode, the device has the proper operational throughput to perform all
required computations as long as MCLK is
≥128 LRCLK. But there is no longer the requirement that MCLK be
harmonically related to SCLK and LRCLK. Values of MCLK could be chosen such that the output dithers between
latencies of 1.5 and 2.5 sample times. There may be cases where part of the data stream output exhibits sample time
latencies of 1.5 Ts and the other portion of the output data stream exhibits sample time latencies of 2.5 Ts . To assure
that such cases do not happen in the I2S slave mode, the relationships between MCLK and LRCLK given in Table 21
should be followed for data format conversions involving the I2S format. The MCLKI/XTALI frequencies given in
Table 21 (if set to within
±5% of the nominal value shown) assure that the DAP processing time falls above 0.5 Ts
or below 0.5 Ts with enough margin to assure that there is no race condition between the outputting of data and the
completion of the processing tasks.
Table 21. TAS3103 Throughput Latencies vs MCLK and LRCLK
AUDIO
SAMPLE RATE
(LRCLK)
MASTER CLOCK(2)
(MCLKI/XTALI)
DAP(1) CLOCK
(PLL_OUTPUT)
DAP CLOCK
CYCLES/LRC
LK
DAP
PROCESSING
TIME
THROUGHPU
T DELAY
96 kHz
24.576 MHz, 12.288 MHz
135.168 MHz
1408
> Ts/2
2.5 Ts
88.2 kHz
22.5792 MHz, 11.2896 MHz
124.1856 MHz
1408
> Ts/2
2.5 Ts
48 kHz
24.576 MHz, 12.288 MHz
135.168 MHz
2816
< Ts/2
1.5 Ts
48 kHz
24.576 MHz, 12.288 MHz, 6.144 MHz
67.584 MHz
1408
> Ts/2
2.5 Ts
44.1 kHz
22.5792 MHz, 11.2896 MHz
124.1856 MHz
2816
< Ts/2
1.5 Ts
44.1 kHz
22.5792 MHz, 11.2896 MHz, 5.6448 MHz
62.0928 MHz
1408
> Ts/2
2.5 Ts
32 kHz
16.384 MHz, 8.192 MHz
90.112 MHz
2816
< Ts/2
1.5 Ts
32 kHz
16.384 MHz, 8.192 MHz, 4.096 MHz
45.056 MHz
1408
> Ts/2
2.5 Ts
24.576 MHz, 12.2858 MHz
135.168 MHz
5632
< Ts/2
1.5 Ts
24 kHz
24.576 MHz, 12.2858 MHz, 6.144 MHz
67.584 MHz
2816
< Ts/2
1.5 Ts
24 kHz
12.288 MHz, 6.144 MHz, 3.072 MHz
33.792 MHz
1408
> Ts/2
2.5 Ts
22.5792 MHz, 11.2896 MHz
124.1856 MHz
5632
< Ts/2
1.5 Ts
22.05 kHz
22.5792 MHz, 11.2896 MHz, 5.6448 MHz
62.0928 MHz
2816
< Ts/2
1.5 Ts
22.05 kHz
11.2896 MHz, 5.6448 MHz, 2.8224 MHz
31.0464 MHz
1408
> Ts/2
2.5 Ts
24.576 MHz, 12.288 MHz
135.168 MHz
16896
< Ts/2
1.5 Ts
8 kHz
24.576 MHz, 12.288 MHz, 6.144 MHz
67.584 MHz
8448
< Ts/2
1.5 Ts
8 kHz
12.288 MHz, 6.144 MHz, 3.072 MHz
33.792 MHz
4224
< Ts/2
1.5 Ts
6.144 MHz, 3.072 MHz, 1.536 MHz
16.896 MHz
2112
> Ts/2
2.5 Ts
NOTES:
1. DAP clock is the internal digital audio processor clock. It is equal to 11
× MCLK1/XTALI, 11/2 × MCLKI/XTALI, or 11/4 × MCLKI/XTALI
(as determined by a bit field in I2C subaddress 0xF9). The DAP clock must always be greater than or equal to 1400 FS (LRCLK).
2. Unless in PLL bypass, MCLKI must be
≤ 20 MHz.
3. XTALI must always be
≤ 20 MHz.
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