- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98158 > TAS3103DBTR (TEXAS INSTRUMENTS INC) SPECIALTY CONSUMER CIRCUIT, PDSO38 PDF資料下載
參數(shù)資料
| 型號(hào)： | TAS3103DBTR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| 封裝： | GREEN, PLASTIC, TSSOP-38 |
| 文件頁(yè)數(shù)： | 97/148頁(yè) |
| 文件大?。?/td> | 1247K |
| 代理商： | TAS3103DBTR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)當(dāng)前第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)
221
Table 25. Four Byte Read Exceptions—Reserved and Factory-Test I2C Subaddresses
SUB-ADDRESS
NUMBER BYTES SUPPLIED BY TAS3103
0xC9
8
0xED
8
NOTE: Table 25 does not include read-only subaddresses and thus does
not include subaddresses 0xFD, 0xFE, and 0xFF. When read, these
read-only subaddresses output 10, 2, and 1 byte respectively.
Thus, for all reserved and factory-test subaddresses, except subaddresses OxC9 and 0xED, the master device must
issue four data received acknowledges for the four bytes of zero-valued data. For subaddresses OxC9 and 0xED,
the master device must issue eight data received acknowledges for the eight bytes of zero-valued data.
Sequential read transactions do not have restrictions on outputting only complete subaddress data sets. If the master
does not issue enough data received acknowledges to receive all the data for a given subaddress, the master device
simply does not receive all the data. If the master device issues more data received acknowledges than required to
receive the data for a given subaddress, the master device simply receives complete or partial sets of data, depending
on how many data received acknowledges are issued from the subaddress(es) that follow.
I2C read transactions, both sequential and random, can impose wait states. For the standard I2C mode
(SCL = 100 kHz), worst-case wait state times for an 8-MHz microprocessor clock is on the order of 2
s. Nominal
wait state times for the same 8-MHz microprocessor clock is on the order of 1
s. For the fast I2C mode (SCL =
400 kHz) and the same 8-MHz microprocessor clock, worst-case wait state times can extend up to 10.5
s in duration.
Nominal wait state times for this same case lie in a range from 2
s to 4.6 s. Increasing the microprocessor clock
frequency lowers the wait state times and for the standard I2C mode, a higher microprocessor clock can totally
eliminate the presence of wait states. For example, increasing the microprocessor clock to 16 MHz results in no wait
states. For the fast I2C mode, higher microprocessor clocks shortens the wait state times encountered, but does not
totally eliminate their presence.
2.4
Digital Audio Processor (DAP) Arithmetic Unit
The digital audio processor (DAP) arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit
and data and coefficient memory blocks. Figure 217 is a block diagram of the arithmetic unit.
76-Bit Adder
Regs
Arithmetic
Engine
Dual Port
Data RAM
Coefficient
RAM
4K x 16
Delay Line
RAM
Program
ROM
DAP
Instruction Decoder/Sequencer
Digital Audio Processor
(DAP)
Arithmetic Unit
Figure 217. Digital Audio Processor Arithmetic Unit Block Diagram
The DAP arithmetic unit is used to implement all firmware functions—soft volume, loudness compensation, bass and
treble processing, dynamic range control, channel filtering, 3D effects, input and output mixing, spectrum analyzer,
VU meter, and dither.
Figure 218 shows the data word structure of the DAP arithmetic unit. Eight bits of overhead or guard bits are provided
at the upper end of the 48-bit DAP word and 8 bits of computational precision or noise bits are provided at the lower
end of the 48-bit word. The incoming digital audio words are all positioned with the most significant bit abutting the
8-bit overhead/guard boundary. The sign bit in bit 39 indicates that all incoming audio samples are treated as signed
data samples.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TAS3103IDBTRG4 | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| TAS3103IDBTR | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| TAS3103IDCP | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| TAS3103DBTG4 | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| TAS3202PAGR | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS3103DBTRG4 | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3103EVM | 功能描述:音頻 DSP TAS3103 Eval Mod RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3103IDBT | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3103IDBTR | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3103IDBTRG4 | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。