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參數(shù)資料
| 型號： | TAS3103EVM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Evaluation Module for Digital Audio Processor With 3D Effects(帶3維效果的數(shù)字音頻處理器TAS3103的評估模塊) |
| 中文描述： | 評估模塊用于數(shù)字音頻處理器，3D音效（帶3維效果的數(shù)字音頻處理器TAS3103的評估模塊） |
| 文件頁數(shù)： | 14/22頁 |
| 文件大小： | 90K |
| 代理商： | TAS3103EVM |
MCLK Routing Switches
2-4
The TAS3103 can format all output channels on one TMD data stream. The
output port used by the TAS3103 for this formatting option is SDOUT1. When
both TAS3103s are being used and both are formatted to output a single TDM
data stream, an option exists where both TDM data streams can be combined
into a single TDM output data stream. In the EVM architecture, SDOUT1 of the
TAS3103
–
U1 is chosen to be this data stream. The TDM output from the
TAS3103
–
U2 is merged into this composite TDM data stream by connecting
SDOUT1 of TAS3103
–
U2 to the ORIN input of the TAS3103
–
U1. Setting S18
to H enables this option. If ORIN of TAS3103
–
U1 is not used, S18 must be set
to L.
For the I
2
S output header and the PCM1606 DAC, outputs SDOUT1 and
SDOUT2 are always sourced by TAS3103
–
U1, but SDOUT3 can be sourced
by either SDOUT2 of the TAS3103
–
U2 (S6 set to H) or SDOUT3 of
TAS3103
–
U1 (S6 set to L). The SPDIF Tx always outputs SDOUT1 of the
TAS3103
–
U1.
2.2
MCLK Routing Switches
Figure 2
–
3 illustrates the MCLK options provided by the EVM. There are three
choices for sourcing MCLK
–
SPDIF Rx, I
2
S input header, and TAS3103
–
U1.
S5 selects between the SPDIF Rx MCLK (S5 = L) and an I
2
S input port
supplied MCLK (S5 = H). For the EVM architecture, if the SPDIF Rx is being
used as a source of input data, MCLK, SCLK, and LRCLK from the SPDIF Rx
must serve as the system clocks. The SPDIF Rx must always serve as clock
master when used. If an MCLK from an input device connected to the I
2
S input
port is being used as the system MCLK, S8 must be set to H to place the driver
used in a 3-state condition to output MCLK to an input device connected to the
I
2
S input port.
The S5 switch selection is routed to an AND gate, where it is gated with the
S1 switch setting. If TAS3103
–
U1 is to be supplied an MCLK (TAS3103
–
U1
is a slave device), S1 must be set to H to allow the selected MCLK to pass
through the AND gate to pin MCLKI of TAS3103
–
U1. Also, in this case, a shunt
must be attached to JP11 to disable the XTALI pin.
If TAS3103
–
U1 is to serve as the source of MCLK, the crystal resource
connected to pins XTALI and XTALO must be used to derive MCLK. In the
TAS3103, MCLKI and XTALI are OR
’
ed together and thus it is necessary that
MCLKI be driven with a logic 0 signal when not being supplied an external
MCLK. In this case, then, S1 must be set to L, and the shunt must be removed
from JP11.
MCLKO of TAS3103
–
U1 is used to source MCLK for all devices on the EVM
other than the SPDIF Rx, regardless of whether or not TAS3103
–
U1 is the
source of MCLK. In the TAS3103 power-up default state, MCLKO = (MCLKI
OR XTALI). Subsequent I
2
C commands can be issued to the TAS3103 to set
MCLKO to (MCLKI OR XTALI)/2 or (MCLKI OR XTALI)/4. But for the EVM
architecture, MCLKO must always be set to (MCLKI OR XTALI) if either the
output DAC, the input ADCs, or the SPDIF Tx is being used.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TAS3103IDBT | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS3103IDBTR | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS3103IDBTRG4 | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS3108 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:AUDIO DIGITAL SIGNAL PROCESSORS |
| TAS3108DCP | 功能描述:音頻 DSP 8-Channel Audio DSP RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
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