參數(shù)資料
型號(hào): TAS3103EVM
廠商: Texas Instruments, Inc.
英文描述: Evaluation Module for Digital Audio Processor With 3D Effects(帶3維效果的數(shù)字音頻處理器TAS3103的評(píng)估模塊)
中文描述: 評(píng)估模塊用于數(shù)字音頻處理器,3D音效(帶3維效果的數(shù)字音頻處理器TAS3103的評(píng)估模塊)
文件頁(yè)數(shù): 18/22頁(yè)
文件大?。?/td> 90K
代理商: TAS3103EVM
LRCLK Routing Switches
2-8
SCLKOUT1 of TAS3103
U1 serves as the SCLK for the ADCs and
SCLKOUT2 of TAS3103
U1 serves as the SCLK for the 6-channel DAC and
the SPDIF Tx. Both SCLKOUT clocks are routed to a multiplexer. Switch S11
selects whether SCLKOUT1 of TAS3103
U1 (S11 set to L) or SCLKOUT2 of
TAS3103
U1 (S11 set to H) is routed to pin SCLKIN of TAS3103
U2. This
multiplexer is necessary as either clock can be the higher frequency clock in
certain applications and SCLKIN must be provided the higher of the two
clocks.
If TAS3103
U1 is the master and provides SCLK to an external device on the
I
2
S input port, switch S9 must be set to L to enable the gate driving SCLK to
the external device. When the TAS3103 is a master, the signal on pin SCLKIN
is not used, and thus the state of the signal into the pin is not an issue.
2.4
LRCLK Routing Switches
Figure 2
5 illustrates the LRCLK options provided by the EVM. There are
three choices for sourcing LRCLK
SPDIF Rx, I
2
S input header, and
TAS3103
U1. Again, if the SPDIF Rx is used to source LRCLK, it must also
source MCLK and SCLK.
S3 selects between the SPDIF Rx LRCLK (S3 = H) and an I
2
S input port
LRCLK (S3 = L). If the I
2
S input port is used to source LRCLK, S9 must be set
to H to place in a 3-state condition the driver used to supply LRCLK to an input
device connected to the I
2
S input port. (Note that S3 and S9 served the same
functions for SCLK).
The output of the S3 selection is routed to a buffer whose output is controlled
by switch S7. In the TAS3103, LRCLK is a bidirectional pin. When the TAS3103
is serving as clock master, any devices driving this pin must be placed in a
3-state condition. When S7 is set to H, the driver is placed in the 3-state
condition.
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