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參數(shù)資料
| 型號(hào)： | TAS3103IDBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| 封裝： | GREEN, PLASTIC, TSSOP-38 |
| 文件頁(yè)數(shù)： | 35/148頁(yè) |
| 文件大?。?/td> | 1247K |
| 代理商： | TAS3103IDBT |
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16
TERMINAL
PULLUP/
DOWN(2)
DESCRIPTION
NAME
PULLUP/
DOWN(2)
DESCRIPTION
TYPE(1)
I/O
NO.
I2C_SCL
13
I/O
D
I2C_SCL is the I2C clock pin. When the TAS3103 I2C port is a master,
I2C_SCL is (1/2N) x (1/(M+1)) x 1/10 times the microprocessor clock, where N
and M are set to 2 and 8 respectively. When the TAS3103 I2C port is a slave,
input clock rates up to 400 kHz can be supported. This pin must be provided an
external pullup (5 k
is recommended for most applications).
External
pullup
required
I2C_SDA
12
I/O
D
I2C_SDA is the I2C bidirectional data pin. The TAS3103 I2C port can support
data rates up to 400K bits/sec. This pin must be provided an external pullup
(5 k
is recommended for most applications).
External
pullup
required
LRCLK
38
I/O
D
LRCLK is either an input or an output, depending on whether the TAS3103 is in
a master or slave serial audio port mode, which is determined by bit 22 of
subaddress 0xF9.
Pulldown
MCLKI
9
I
D
MCLKI is a master clock input that provides an alternative to using a fixed
crystal frequency. In DPLL modes, the input frequency of this clock can range
from 2.8 MHz to 24.576 MHz. In PLL bypass mode, frequencies up to 136 MHz
can be used. Whenever MCLKI is not used and XTALI/XTALO provide the
master clock input, MCLKI must be grounded.
None
MCLKO
34
O
D
MCLKO is the master output clock pin. It is produced by dividing MCLKI/XTALI
by 1, 2, or 4 (depending on the setting of a subaddress control field). MCLKO is
provided to interconnect, without the need for additional glue logic, the
TAS3103 interfaces chips that require different multiples of the audio sample
rate (FS) as a master clock.
None
MICROCLK_DIV
11
I
D
MICROCLK_DIV sets the division ratio between the digital audio processing
clock and the internal microprocessor clock. The audio-processing clock is the
DPLL output clock if PLL_bypass is not enabled. The audio-processing clock
is MCLKI/XTALI master clock if PLL_bypass is enabled. Logic high on this pin
sets the microprocessor clock equal to the audio-processing clock. A logic low
sets the microprocessor clock to 1/4 the digital audio-processing clock.
MICROCLK_DIV must be set low if the audio processing clock is > 36 MHz.
MICROCLK_DIV must be set high if the audio processing clock is
≤ 36 MHz.
Pulldown
ORIN
37
I
D
ORIN allows the processing of a multichannel signal set through two
TAS3103s without any additional components. One use of ORIN would be to
fully emulate a 6-channel audio processor at speeds up to a 96-kHz sample
rate with only two TAS3103s and no glue logic.
The two-chip configuration is accomplished by wiring the SDOUT1 port of one
of the two TAS3103 chips to the ORIN port of the second TAS3103. Internal to
the chip, the ORIN input is OR’ed with internal SDOUT1 data to generate the
resulting output data on channel SDOUT1. For TDM output formats, the
SDOUT1 outputs of the two chips differ in phasing in both the left and right
channels to arrive at the proper composite output. For discrete outputs, one
chip contributes the left channel of the composite SDOUT1, and the other chip
contributes the right channel of the composite SDOUT1.
If not used, ORIN must be connected to ground.
Pulldown
PLL0
22
I
D
PLL0 is the LSB of a 2-bit code used to select four different modes of DPLL
multiplexer/input divider operation. PLL[1:0] values of 00, 01, and 10 select
the DPLL input clock to be MCLKI/XTALI divided by 1, 2, and 4 respectively. A
value of 11 results in MCLKI/XTALI being substituted for the DPLL output. The
pullup/pulldown combination provides a default of 01 when neither pin is
connected.
Pullup
PLL1
23
I
D
PLL1 is the MSB of a 2-bit code used to select four different modes of DPLL
multiplexer/input divider operation. PLL[1:0] values of 00, 01, and 10 select
the DPLL input clock to be MCLKI/XTALI divided by 1, 2, and 4 respectively. A
value of 11 results in MCLKI/XTALI being substituted for the DPLL output. The
pullup/pulldown combination provides a default of 01 when neither pin is
connected.
Pulldown
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| TAS3103IDBTR | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| TAS3103IDCP | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS3103IDBTR | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3103IDBTRG4 | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3108 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:AUDIO DIGITAL SIGNAL PROCESSORS |
| TAS3108DCP | 功能描述:音頻 DSP 8-Channel Audio DSP RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3108DCPG4 | 功能描述:音頻 DSP 8-Channel Audio DSP RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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