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參數(shù)資料
| 型號(hào)： | TAS3103IDBTRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| 封裝： | GREEN, PLASTIC, TSSOP-38 |
| 文件頁(yè)數(shù)： | 99/148頁(yè) |
| 文件大?。?/td> | 1247K |
| 代理商： | TAS3103IDBTRG4 |
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The DAP processing clock is set by pins PLL0 and PLL1, in conjunction with the source clock XTALI or MCLKI. The
DAP operates at speeds up to 136 MHz, which is sufficient to process 96-kHz audio.
2.5
Reset
The reset circuitry in the TAS3103 is shown in Figure 220. A reset is initiated by inputting logic 0 on the reset pin
RST.. A reset is also issued at power turnon by the internal 1.8-V regulator subsystem.
MCLKI
XTALI
DPLL
1.8-V Regulator Subsystem
Reset Timer
CLR
Lock
Chip Reset
VDSS
Enable
dpll_clk
PWR GOOD
RST
A_VDSS
Figure 220. TAS3103 Reset Circuitry
At power turnon, the internal 1.8-V regulator subsystem issues an internal reset that remains active until regulation
is reached. The duration of this signal assures that all reset activities are conducted at power turnon. This means that
the external reset pin RST does not require an RC time constant derived external reset to assure that a reset is applied
at power turnon. The reset pin RST can then be used exclusively for exception resets, saving the cost and size impact
of additional RC components. However, since RST is an asynchronous clear, it can respond to narrow negative signal
transitions. Some applications, therefore, might require a high-frequency capacitor on the RST pin in order to remove
unwanted noise excursions.
2.6
Power Down
Setting the PWRDN pin to logic 1 enables power down. Power down stops all clocks in the TAS3103, but preserves
the state of the TAS3103. When PWRDN is deactivated (set to logic 0) after a period of activation, the TAS3103
resumes the processing of audio data upon receiving the next LRCLK (indicating a new sample of audio data is
available for processing). The configuration of the TAS3103 and all programmable parameters are retained during
power down.
There is a time lag between setting PWRDN to logic 1 and entering the power down state. PWRDN is sampled every
GPIOFSCOUNT LRCLK periods (see the subaddress 0xEF and the watchdog timer and GPIO ports sections). This
means that a time lag as great as GPIOFSCOUNT(1/LRCLK) could exist between the activation of PWRDN (setting
to logic 1) and the time at which the microprocessor recognizes that the PWRDN pin has been activated. Normally,
upon recognizing that the PWRDN pin has been activated, the TAS3103 enters the power-down state approximately
80 microprocessor clock cycles later. However, if a soft volume update is in progress, the TAS3103 waits until the
soft volume update is complete before entering the power down state. For this case then, the worst case time lag
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| TAS3108 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:AUDIO DIGITAL SIGNAL PROCESSORS |
| TAS3108DCP | 功能描述:音頻 DSP 8-Channel Audio DSP RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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