參數(shù)資料
型號(hào): TAS5036B
廠商: Texas Instruments, Inc.
英文描述: Digital Audio PWM Processor
中文描述: 數(shù)字音頻 PWM 處理器
文件頁數(shù): 37/56頁
文件大?。?/td> 713K
代理商: TAS5036B
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
31
SLES073
February 2003
TAS5036B
< 2 ms
MCLK
RESET
ERR_RCVRY
ERR_RCVRY and MUTE can
be set at any time prior to 2 ms
following the low-to-high
transistion of RESET
MUTE
Wait a minimum of 100
μ
s
after the low-to-high
transistion of RESET
> 5 ms
Set serial interface format, data rate,
volume, ... via I2C
Release ERR_RCVRY and
then MUTE when I2C
registers are programmed
Volume ramp
up 120 ms
Figure 4
2. Extending the I
2
C Write Interval Following a Low-to-High Transition of the RESET Terminal
The operation of the TAS5036B can be tailored as desired to meet specific operating requirements by
adjusting the following:
Volume
Data sample rate
Emphasis/deemphasis settings
Individual channel mute
Automute delay register
DC-offset control registers
If desired, the TAS5036B can be set to perform an unmute sequence following the low-to-high transition of
the ERR_RCVRY terminal or the error recovery I
2
C command (register X03 bit D2). This capability is set by
writing x7F to the individual error recovery register (x04) and an x84 to x1F (a feature enable register).
4.2
Data Sample Rate
If the master clock is well-behaved during the frequency transition (no MCLK_IN high or low clock periods less
than 20 ns) then a simple speed selection is performed by setting the DBSPD terminal or the serial control
register. If it is known at least 60 ms in advance that the sample rate is going to change, mute can be used
to provide a completely silent transition. The timing of this control sequence is shown in Figure 4
3 and
Figure 4
4.
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