TAS5508B
8-Channel Digital Audio PWM Processor
SLES162C – DECEMBER 2005 – REVISED JULY 2009
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5.4
Multiple-Byte Write
.........................................................................................................
655.5
Incremental Multiple-Byte Write
..........................................................................................
655.6
Single-Byte Read
...........................................................................................................
665.7
Multiple-Byte Read
.........................................................................................................
666
Serial-Control I2C Register Summary
.................................................................................... 67 7
Serial-Control Interface Register Definitions
.......................................................................... 71 7.1
Clock Control Register (0x00)
............................................................................................
717.2
General Status Register 0 (0x01)
........................................................................................
717.3
System Control Register 1 (0x03)
........................................................................................
717.4
System Control Register 2 (0x04)
........................................................................................
727.5
Channel Configuration Control Registers (0x05–0x0C)
...............................................................
727.6
Headphone Configuration Control Register (0x0D)
....................................................................
737.7
Serial Data Interface Control Register (0x0E)
..........................................................................
737.8
Soft Mute Register (0x0F)
.................................................................................................
747.9
Automute Control Register (0x14)
.......................................................................................
757.10
Output Automute PWM Threshold and Back-End Reset Period Register (0x15)
..................................
767.11
Modulation Index Limit Register (0x16)
.................................................................................
777.12
Bank-Switching Command Register (0x40)
.............................................................................
787.13
Input Mixer Registers, Channels 1–8 (0x41–0x48)
....................................................................
797.14
Bass Management Registers (0x49–0x50)
.............................................................................
827.15
Biquad Filter Register (0x51–0x88)
......................................................................................
827.16
Bass and Treble Bypass Register, Channels 1–8 (0x89–0x90)
.....................................................
837.17
Loudness Registers (0x91–0x95)
........................................................................................
837.18
DRC1 Control Registers, Channels 1–7 (0x96)
........................................................................
847.19
DRC2 Control Register, Channel 8 (0x97)
..............................................................................
857.20
DRC1 Data Registers (0x98–0x9C)
.....................................................................................
857.21
DRC2 Data Registers (0x9D–0xA1)
.....................................................................................
867.22
DRC Bypass Registers (0xA2–0xA9)
....................................................................................
867.23
8
×2 Output Mixer Registers (0xAA–0xAF) .............................................................................. 86 7.24
8
×3 Output Mixer Registers (0xB0–0xB1) .............................................................................. 87 7.25
PSVC Volume Biquad Register (0xCF)
.................................................................................
897.26
Volume, Treble, and Bass Slew Rates Register (0xD0)
..............................................................
907.27
Volume Registers (0xD1–0xD9)
..........................................................................................
907.28
Bass Filter Set Register (0xDA)
..........................................................................................
927.29
Bass Filter Index Register (0xDB)
.......................................................................................
937.30
Treble Filter Set Register (0xDC)
........................................................................................
947.31
Treble Filter Index (0xDD)
.................................................................................................
957.32
AM Mode Register (0xDE)
................................................................................................
957.33
PSVC Range Register (0xDF)
............................................................................................
977.34
General Control Register (0xE0)
.........................................................................................
977.35
Incremental Multiple-Byte Write Append Register (0xFE)
............................................................
978
TAS5508B Example Application Schematic
........................................................................... 99 Contents
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