1
Introduction
1.1
Features
TAS5508B
8-Channel Digital Audio PWM Processor
www.ti.com
SLES162C – DECEMBER 2005 – REVISED JULY 2009
L, R, and C
General Features
LS, RS
–
Automated Operation With an Easy-to-Use
LR, RR
Control Interface
Sub
–
I2C Serial-Control Slave Interface
–
Configurable Loudness Compensation
–
Integrated AM Interference-Avoidance
Circuitry
–
Two Dynamic Range Compressors With
Two Thresholds, Two Offsets, and Three
–
Single, 3.3-V Power Supply
Slopes
–
64-Pin TQFP Package
–
Seven Biquads Per Channel
–
5-V Tolerant Inputs
–
Full 8
×8 Input Crossbar Mixer. Each
Audio Input/Output
Signal-Processing Channel Input Can Be
–
Automatic Master-Clock-Rate and
Any Ratio of the Eight Input Channels.
Data-Sample-Rate Detection
–
8
×2 Output Mixer, Channels 1–6. Each
–
Eight Serial Audio Input Channels
Output Is a Mix of Any Two
–
Eight PWM Audio Output Channels
Signal-Processed Channels. It Is
Configurable as Six Channels With Stereo
Recommended to Use the Pass-Through
Lineout or Eight Channels
output Mixer Configuration.
–
Line Output Is a PWM Output to Drive an
–
8
×3 Output Mixer, Channels 7 and 8. Each
External Differential-Input Operational
Output Is a Mix of Any Three
Amplifier
Signal-Processed Channels. It Is
–
Headphone PWM Output to Drive an
Recommended to Use the Pass-Through
External Differential Amplifier Like the
Output Mixer Configuration.
TPA112
–
Three Coefficient Sets Stored on the Device
–
PWM Outputs Support Single-Ended and
Can Be Selected Manually or Automatically
Bridge-Tied Loads
(Based on Specific Data Rates).
–
32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and
–
DC Blocking Filters
192-kHz Sampling Rates
–
Able to Support a Variety of Bass
–
Data Formats: 16-, 20-, or 24-Bit
Management Algorithms
Left-Justified, I2S, or Right-Justified Input
PWM Processing
Data
–
32-Bit Processing PWM Architecture With
–
64-fS Bit-Clock Rate
40 Bits of Precision
–
128-, 192-, 256-, 384-, 512-, and 768-fS
–
8
× Oversampling With Fifth-Order Noise
Master Clock Rates (Up to a Maximum of
Shaping at 32 kHz–48 kHz, 4
×
50 MHz)
Oversampling at 88.2 kHz and 96 kHz, and
Audio Processing
2
× Oversampling at 176.4 kHz and 192 kHz
–
48-Bit Processing Architecture With 76 Bits
–
>102-dB Dynamic Range
of Precision for Most Audio-Processing
–
THD+N < 0.1%
Features
–
20-Hz–20-kHz, Flat Noise Floor for 44.1-,
–
Volume Control Range 36 dB to –109 dB
48-, 88.2-, 96-, 176.4-, and 192-kHz Data
Master Volume Control Range of 18 dB
Rates
to –109 dB
–
Digital De-Emphasis for 32-, 44.1-, and
Eight Individual Channel Volume Control
48-kHz Data Rates
Ranges of 18 dB to –109 dB
–
Flexible Automute Logic With
–
Programmable Soft Volume and Mute
Programmable Threshold and Duration for
Update Rates
Noise-Free Operation
–
Four Bass and Treble Tone Controls With
–
Intelligent AM Interference-Avoidance
±18-dB Range, Selectable Corner
System Provides Clear AM Reception
Frequencies, and Second-Order Slopes
–
Power-Supply Volume Control (PSVC)
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Instruments semiconductor products and disclaimers thereto appears at the end of this document.
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PRODUCTION DATA information is current as of publication date.
Copyright 2005–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.