參數(shù)資料
型號： TAS5508PAG
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁數(shù)： 29/105頁
文件大?。?/td> 1286K
代理商： TAS5508PAG
TAS5508
8-Channel Digital Audio PWM Processor
www.ti.com
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
3.2.3
Back-End Error (BKND_ERR)
................................................................................. 46
3.2.4
Speaker/Headphone Selector (HP_SEL)
..................................................................... 46
3.2.5
Mute (MUTE)
..................................................................................................... 46
3.3
Device Configuration Controls
............................................................................................ 47
3.3.1
Channel Configuration Registers
.............................................................................. 47
3.3.2
Headphone Configuration Registers
.......................................................................... 48
3.3.3
Audio System Configurations
.................................................................................. 48
3.3.3.1
Using Line Outputs in 6-Channel Configurations
................................................. 49
3.3.4
Recovery from Clock Error
..................................................................................... 49
3.3.5
Power-Supply Volume-Control Enable
....................................................................... 49
3.3.6
Volume and Mute Update Rate
................................................................................ 49
3.3.7
Modulation Index Limit
.......................................................................................... 50
3.3.8
Interchannel Delay
.............................................................................................. 50
3.4
Master Clock and Serial Data Rate Controls
........................................................................... 50
3.4.1
PLL Operation
.................................................................................................... 51
3.5
Bank Controls
............................................................................................................... 51
3.5.1
Manual Bank Selection
......................................................................................... 52
3.5.2
Automatic Bank Selection
...................................................................................... 52
3.5.2.1
Coefficient Write Operations While Automatic Bank Switch Is Enabled
....................... 52
3.5.3
Bank Set
.......................................................................................................... 52
3.5.4
Bank-Switch Timeline
........................................................................................... 52
3.5.5
Bank-Switching Example 1
..................................................................................... 53
3.5.6
Bank-Switching Example 2
..................................................................................... 53
4
Electrical Specifications
...................................................................................................... 55
4.1
Absolute Maximum Ratings
............................................................................................... 55
4.2
Dissipation Rating Table (High-k Board, 105
＝C Junction)
................................................ 55
4.3
Dynamic Performance At Recommended Operating Conditions at 25
＝C
.............................. 55
4.4
Recommended Operating Conditions
........................................................................ 55
4.5
Electrical Characteristics
....................................................................................... 56
4.6
PWM Operation
.................................................................................................. 56
4.7
Switching Characteristics
....................................................................................... 56
4.7.1
Clock Signals
..................................................................................................... 56
4.7.2
Serial Audio Port
................................................................................................. 57
4.7.3
I
2C Serial Control Port Operation
.............................................................................. 58
4.7.4
Reset Timing (RESET)
......................................................................................... 59
4.7.5
Power-Down (PDN) Timing
.................................................................................... 59
4.7.6
Back-End Error (BKND_ERR)
................................................................................. 60
4.7.7
Mute Timing (MUTE)
............................................................................................ 60
4.7.8
Headphone Select (HP_SEL)
.................................................................................. 61
4.7.9
Volume Control
.................................................................................................. 62
4.8
Serial Audio Interface Control and Timing
................................................................... 62
4.8.1
I
2S Timing
........................................................................................................ 62
4.8.2
Left-Justified Timing
............................................................................................. 63
4.8.3
Right-Justified Timing
........................................................................................... 64
5
I2C Serial-Control Interface (Slave Address 0x36)
................................................................... 65
5.1
General I
2C Operation
..................................................................................................... 65
5.2
Single- and Multiple-Byte Transfers
..................................................................................... 65
5.3
Single-Byte Write
........................................................................................................... 66
5.4
Multiple-Byte Write
......................................................................................................... 66
5.5
Incremental Multiple-Byte Write
.......................................................................................... 67
5.6
Single-Byte Read
........................................................................................................... 67
5.7
Multiple-Byte Read
......................................................................................................... 68
Contents
3
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