參數(shù)資料
型號(hào): TAS5508PAG
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù): 65/105頁(yè)
文件大?。?/td> 1286K
代理商: TAS5508PAG
4.7.9
Volume Control
4.8
Serial Audio Interface Control and Timing
4.8.1
I
2S Timing
23
22
SCLK
32Clks
LRCLK(NoteReversedPhase)
LeftChannel
24-BitMode
1
19
18
20-BitMode
16-BitMode
15
14
MSB
LSB
32Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput
2
T0034-01
5
4
9
8
1
0
4
5
1
0
23
22
1
19
18
15
14
MSB
LSB
5
4
9
8
1
0
4
5
1
0
SCLK
TAS5508
8-Channel Digital Audio PWM Processor
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
www.ti.com
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Individual volume, master volume, or a
Maximum attenuation before mute
–127
dB
combination of both
Maximum gain
Individual volume, master volume
18
dB
Maximum volume before the onset of clipping
0-dB input, any modulation limit
0
dB
PSVC range
PSVC enabled
12, 18, or 24
dB
PSVC rate
Fs
PSVC modulation
Single sided
PSVC quantization
2048
Steps
6%
95%
PSVC PWM modulation limits
PSVC range = 24 dB
dB
(120 : 2048)
(1944 : 2048)
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 64
= Fs is
used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the
first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS5508 masks unused trailing data bit positions.
Figure 4-9. I2S 64-Fs Format
Electrical Specifications
62
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