參數(shù)資料
型號: TAS5508PAGG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 83/105頁
文件大?。?/td> 1286K
代理商: TAS5508PAGG4
7.12 Modulation Index Limit Register (0x16)
7.13 Interchannel Delay Registers (0x1B–0x22)
7.14 Channel Offset Register (0x23)
7.15 Bank-Switching Command Register (0x40)
TAS5508
8-Channel Digital Audio PWM Processor
www.ti.com
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
Bits D7–D3 are Don't Care.
Table 7-12. Modulation Index Limit Register Format
LIMIT
MIN WIDTH
MODULATION
D7
D6
D5
D4
D3
D2
D1
D0
[DCLKs]
INDEX
0
1
2
99.2%
0
1
2
4
98.4%
0
1
0
3
6
97.7%
0
1
4
8
96.9%
1
0
5
10
96.1%
1
0
1
6
12
95.3%
1
0
7
14
94.5%
1
8
16
93.8%
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, and 0x22,
respectively.
Bits D1 and D0 are Don't Care.
Table 7-13. Interchannel Delay Register Format
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
Minimum absolute delay, 0 DCLK cycles, default for channel 1
0
1
Maximum positive delay, 31
= 4 DCLK cycles
1
0
Maximum negative delay, –32
= 4 DCLK cycles
1
0
Default value for channel 1 = –32
0
Default value for channel 2 = 0
1
0
Default value for channel 3 = –16
0
1
0
Default value for channel 4 = 16
1
0
1
0
Default value for channel 5 = –24
0
1
0
Default value for channel 6 = 8
1
0
Default value for channel 7 = –8
0
1
0
Default value for channel 8 = 24
The channel offset register is mapped into 0x23.
Table 7-14. Channel Offset Register Format
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
Minimum absolute offset, 0 DCLK cycles, default for channel 1
1
Maximum absolute offset, 255 DCLK cycles
Bits D31–D24, D22–D19 are Don't Care.
Serial-Control Interface Register Definitions
79
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