3.2.3.1 BKND_ERR and VALID
3.2.4
Speaker/Headphone Selector (HP_SEL)
3.2.5
Mute (MUTE)
TAS5518C
8-Channel Digital Audio PWM Processor
www.ti.com
SLES238A – SEPTEMBER 2008 – REVISED JULY 2009
Table 3-4. Device Outputs During Back-End Error
SIGNAL
SIGNAL STATE
Valid
Low
PWM P-outputs
M-state = low
PWM M-outputs
M-state = low
PWM_HP P-outputs
M-state = low
PWM_HP M-outputs
M-state = low
SDA
Signal input (not driven)
The number of channels that are affected by the BKND_ERR signal depends on the setting of bit D1 of
I2C register 0xE0. If the I2C setting is 0 (8-channel mode), the TAS5518C places all eight PWM outputs in
the PWM back-end error state. If the I2C setting is 1, the TAS5518C is in 6-channel mode. For proper
operation in 6-channel mode, the lineout configuration registers (0x09 and 0x0A) must be 0x00 instead of
the default of 0xE0. In this case, VALID is pulled LOW, and the TAS5518C brings PWM outputs 1, 2, 3, 4,
7, and 8 to a back-end error state, while not affecting lineout channels 5 and 6.
Table 3-4 shows the
device output signal states during back-end error.
The HP_SEL terminal enables the headphone output or the speaker outputs. The headphone output
receives the processed data output from DAP and PWM channels 1 and 2.
In 6-channel configuration, this feature does not affect the two lineout channels.
When low, the headphone output is enabled. In this mode, the speaker outputs are disabled. When high,
the speaker outputs are enabled and the headphone is disabled.
Changes in the pin logic level result in a state change sequence using soft mute to the hard-mute state
(M-state) for both speaker and headphone followed by a soft unmute.
When HP_SEL is low, the configuration of channels 1 and 2 is defined by the headphone configuration
register. When HP_SEL is high, the channel-1 and -2 configuration registers define the configuration of
channels 1 and 2.
If using the remapped-output mixer configuration (0xD0 bit 30 = 0) in the 6-channel mode, the headphone
operation is modified. That is, following the assertion or de-assertion of headphone, mute must be
asserted and de-asserted using the MUTE pin.
The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp
to previous volume. The TAS5518C has both master and individual channel mute commands. A terminal
is also provided for the master mute. The active-low master mute I2C register and the MUTE terminal are
logically ORed together. If either is set to low, a mute on all channels is performed. The master mute
command operates on all channels regardless of whether the system is in the 6- or 8-channel
configuration.
When mute is invoked, the PWM output stops switching and then goes to an idle state.
The master mute terminal is used to support a variety of other operations in the TAS5518C, such as
setting the the biquad coefficients, the serial interface format, and the clock rates. A mute command by the
master mute terminal, individual I2C mute, the AM interference mute sequence, the bank-switch mute
sequence, or automute overrides an unmute command or a volume command. While a mute is active, the
commanded channels are placed in a mute state. When a channel is unmuted, it goes to the last
commanded volume setting that has been received for that channel.
TAS5518C Controls and Status
45