5.4
Multiple-Byte Write
D7
D0 ACK
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
LastDataByte
A6
A5
A1
A0 R/W ACK A7
A5
A1
A0
ACK D7
ACK
Start
Condition
Acknowledge
FirstDataByte
A4
A3
A6
OtherDataBytes
ACK
Acknowledge
D0
D7
D0
T0036-02
5.5
Incremental Multiple-Byte Write
TAS5518C
8-Channel Digital Audio PWM Processor
www.ti.com
SLES238A – SEPTEMBER 2008 – REVISED JULY 2009
A multiple-byte, data-write transfer is identical to a single-byte, data-write transfer except that multiple data
bytes are transmitted by the master device to TAS5518C, as shown in
Figure 5-3. After receiving each
data byte, the TAS5518C responds with an acknowledge bit.
Figure 5-3. Multiple-Byte Write Transfer
The I2C supports a special mode which permits I2C write operations to be broken up into multiple data
write operations that are multiples of four data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc.,
write operations that are composed of a device address, read/write bit, subaddress, and any multiple of
four bytes of data. This permits the system to write large register values incrementally without blocking
other I2C transactions.
This feature is enabled by the append subaddress function in the TAS5518C. This function enables the
TAS5518C to append four bytes of data to a register that was opened by a previous I2C register write
operation but has not received its complete number of data bytes. Because the length of the long registers
is a multiple of four bytes, using four-byte transfers has only an integral number of append operations.
When the correct number of bytes has been received, the TAS5518C starts processing the data.
The procedure to perform an incremental multibyte-write operation is as follows:
1. Start a normal I2C write operation by sending the device address, write bit, register subaddress, and
the first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this
point, the register has been opened and accepts the remaining data that is sent by writing four-byte
blocks of data to the append subaddress (0xFE).
2. At a later time, one or more append data transfers are performed to incrementally transfer the
remaining number of bytes in sequential order to complete the register write operation. Each of these
append operations is composed of the device address, write bit, append subaddress (0xFE), and four
bytes of data followed by a stop condition.
3. The operation is terminated due to an error condition, and the data is flushed:
a.
If a new subaddress is written to the TAS5518C before the correct number of bytes are written.
b.
If more or fewer than four bytes are data written at the beginning or during any of the append
operations.
c.
If a read bit is sent.
65
I2C Serial-Control Interface (Slave Addresses 0x36 and 0x37)