參數(shù)資料
型號: TAS5518CPAGR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 54/103頁
文件大?。?/td> 2007K
代理商: TAS5518CPAGR
4.6
Switching Characteristics
4.6.1
Clock Signals
4.6.2
Serial Audio Port
t
h1
t
su1
t
su2
t
h2
SCLK
(Input)
LRCLK
(Input)
SDIN1
SDIN2
SDIN3
T0026-01
TAS5518C
8-Channel Digital Audio PWM Processor
SLES238A – SEPTEMBER 2008 – REVISED JULY 2009
www.ti.com
PLL input parameters and external filter components over recommended operating conditions (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fXTALI
Frequency, XTAL IN
Only use 13.5-MHz crystal
≤1000 ppm
13.5
MHz
fMCLKI
Frequency, MCLK (1/tcyc2)
2
50
MHz
MCLK duty cycle
40%
50%
60%
≥2-V MCLK = 49.152 MHz, within the min
MCLK minimum high time
5
ns
and max duty cycle constraints
≤0.8-V MCLK = 49.152 MHz, within the min
MCLK minimum low time
5
ns
and max duty cycle constraints
LRCLK allowable drift before LRCLK reset
10
MCLKs
External PLL filter capacitors C11 and C12
SMD 0603 Y5V
100
nF
External PLL filter capacitors C10 and C13
SMD 0603 Y5V
10
nF
External PLL filter resistors R10 and R11
SMD 0603, metal film
200
External VRA_PLL decoupling C14
SMD, Y5V
100
nF
(1)
See the TAS5518C Example Application Schematic, Section 8.
Serial audio port slave mode over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCLKIN SCLK input frequency
CL = 30 pF
2.048
12.288
MHz
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
ns
LRCLK frequency
32
48
192
kHz
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
SCLK
SCLK rising edges between LRCLK rising edges
64
edges
LRCLK clock edge with respect to the falling edge of
SCLK
–1/4
1/4
SCLK
period
Figure 4-1. Slave Mode Serial Data Interface Timing
Electrical Specifications
54
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