參數(shù)資料
型號(hào): TAS5615PHD2EVM
廠商: Texas Instruments
文件頁數(shù): 18/36頁
文件大?。?/td> 0K
描述: EVAL MODULE FOR TAS5615PHD2
標(biāo)準(zhǔn)包裝: 1
系列: *
www.ti.com
SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010
Note T1: PVDD decoupling bulk capacitors C60–C64 should be as close as possible to the PVDD and GND_X pins;
the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and
without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low-impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
Note T3: Heat sink must have a good connection to PCB ground.
Note T4: Output filter capacitors, preferably metal film types, must be linear in the applied voltage range.
Figure 18. Printed Circuit Board – Top Layer
Copyright 2009–2010, Texas Instruments Incorporated
25
Product Folder Link(s) :TAS5615
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