參數(shù)資料
型號: TAS5615PHD2EVM
廠商: Texas Instruments
文件頁數(shù): 2/36頁
文件大?。?/td> 0K
描述: EVAL MODULE FOR TAS5615PHD2
標(biāo)準(zhǔn)包裝: 1
系列: *
SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010
www.ti.com
AUDIO SPECIFICATION (PBTL)
PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 4 , fS = 400 kHz, ROC = 22 k, TC = 75°C, output filter: LDEM = 15 mH, CDEM = 680 nF, MODE =
101-BD, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RL = 4 , 10% THD+N, clipped output signal
300
RL = 6 , 10% THD+N, clipped output signal
210
RL = 8 , 10% THD+N, clipped output signal
160
PO
Power output per channel
W
RL = 4 , 1% THD+N, unclipped output signal
240
RL = 6 , 1% THD+N, unclipped output signal
160
RL = 8 , 1% THD+N, unclipped output signal
125
THD+N
Total harmonic distortion + noise
1 W
0.05
%
Vn
Output integrated noise
A-weighted
260
mV
SNR
Signal-to-noise ratio(1)
A-weighted
100
dB
DNR
Dynamic range
A-weighted
100
dB
Pidle
Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching
(2)
2.3
W
(1)
SNR is calculated relative to 1% THD+N output level.
(2)
Actual system idle losses are affected by core losses of output inductors.
ELECTRICAL CHARACTERISTICS
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
VREG
VDD = 12 V
3
3.3
3.6
V
node
VI_CM
Analog comparator reference node
1.5
1.75
1.9
V
Operating, 50% duty cycle
22.5
IVDD
VDD supply current
mA
Idle, reset mode
22.5
50% duty cycle
8
IGVDD_x
Gate-supply current per half-bridge
mA
Reset mode
1.5
50% duty cycle without output filter or load
7
mA
IPVDD_x
Half-bridge idle current
Reset mode, no switching
610
mA
ANALOG INPUTS
RIN
Input resistance
READY = HIGH
33
k
VIN
Maximum input voltage swing
5
V
IIN
Maximum input current
342
mA
G
Voltage gain (VOUT/VIN)
23
dB
OSCILLATOR
Nominal, master mode
3.85
4
4.15
fOSC_IO+
AM1, master mode
FPWM × 10
3.15
3.33
3.5
MHz
AM2, master mode
2.6
3
3.35
VIH
High-level input voltage
1.86
V
VIL
Low-level input voltage
1.45
V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
120
200
m
TJ = 25°C, includes metallization resistance,
RDS(on)
GVDD = 12 V
Drain-to-source resistance, high side (HS)
120
200
m
10
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TAS5615
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