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參數(shù)資料
| 型號： | TC500COE |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-013, SOIC-16 |
| 文件頁數(shù)： | 38/38頁 |
| 文件大?。?/td> | 562K |
| 代理商： | TC500COE |
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2008 Microchip Technology Inc.
DS21428E-page 9
TC500/A/510/514
4.0
DETAILED DESCRIPTION
4.1
Dual Slope Conversion Principles
Actual data conversion is accomplished in two
phases: input signal integration and reference voltage
de-integration.
The integrator output is initialized to 0V prior to the start
of integration. During integration, analog switch S1
connects VIN to the integrator input where it is
maintained for a fixed time period (TINT). The
application of VIN causes the integrator output to depart
0V at a rate determined by the magnitude of VIN and a
direction determined by the polarity of VIN. The de-
integration phase is initiated immediately at the
expiration of TINT.
During de-integration, S1 connects a reference voltage
(having a polarity opposite that of VIN) to the integrator
input. At the same time, an external precision timer is
started. The de-integration phase is maintained until
the comparator output changes state, indicating the
integrator has returned to its starting point of 0V. When
this occurs, the precision timer is stopped. The de-
integration time period (TDEINT), as measured by the
precision timer, is directly proportional to the magnitude
of the applied input voltage (see Figure 4-3).
A simple mathematical equation relates the input
signal, reference voltage and integration time:
EQUATION 4-1:
For a constant VIN:
EQUATION 4-2:
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle.
An inherent benefit is noise immunity. Input noise
spikes are integrated (averaged to zero) during the
integration periods. Integrating ADCs are immune to
the large conversion errors that plague successive
approximation converters in high noise environments.
Integrating converters provide inherent noise rejection
with at least a 20dB/decade attenuation rate.
Interference signals with frequencies at integral
multiples of the integration period are, theoretically,
completely removed, since the average value of a sine
wave of frequency (1/T) averaged over a period (T) is
zero.
Integrating converters often establish the integration
period to reject 50/60 Hz line frequency interference
signals. The ability to reject such signals is shown by a
normal mode rejection plot (Figure 4-1). Normal mode
rejection is limited in practice to 50 to 65 dB, since the
line frequency can deviate by a few tenths of a percent
(Figure 4-2).
FIGURE 4-1:
Integrating Converter
Normal Mode Rejection.
FIGURE 4-2:
Line Frequency Deviation.
Where:
VREF
=
Reference Voltage
TINT
=
Signal Integration time (fixed)
tDEINT
=
Reference Voltage Integration time
(variable)
1
R
INTCINT
------------------------
V
IN T
()DT
0
T
INT
∫
V
REFCDEINT
R
INTCINT
--------------------------------
=
V
IN
V
REF
T
DEINT
T
INT
------------------
=
30
20
10
0
0.1/T
1/T
10/T
Input Frequency
Normal
Mode
Rejection
(dB)
T = Measurment
Period
0.01
0.1
1.0
Normal
Mode
Rejeciton
(dB)
80
70
60
50
40
30
20
t = 0.1 sec
Line Frequency Deviation from 60 Hz (%)
Normal Mode = 20 LOG
Rejection
DEV = Deviation from 60 Hz
t = Integration Period
SIN 60 t (1 –
)
p
DEV
100
DEV
100
60 t (1 –
)
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