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參數(shù)資料
| 型號(hào)： | TC534CKW |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 28/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DATA ACQ SUBSYSTEM 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 17 b |
| 采樣率（每秒）： | 6.5 |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
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2007 Microchip Technology Inc.
DS21433C-page 9
TC530/TC534
4.0
DETAILED DESCRIPTION
4.1
Dual Slope Integrating Converter
The TC530/TC534 dual slope converter operates by
integrating the input signal for a fixed time period, then
applying an opposite polarity reference voltage while
timing the period (counting clocks pulses) for the
integrator output to cross 0V (deintegrating). The
resulting count is read as conversion data.
A simple mathematical expression that describes dual
slope conversion is:
EQUATION 4-1:
EQUATION 4-2:
from which:
EQUATION 4-3:
And therefore:
EQUATION 4-4:
Inspection of Equation 4-4 shows dual slope converter
accuracy is unrelated to integrating resistor and
capacitor values, as long as they are stable throughout
the measurement cycle. This measurement technique
is inherently ratiometric (i.e., the ratio between the TINT
and TDEINT times is equal to the ratio between VIN and
VREF).
Another inherent benefit is noise immunity. Input noise
spikes are integrated, or averaged to zero, during the
integration period. The integrating converter has a noise
immunity with an attenuation rate of at least -20 dB per
decade. Interference signals with frequencies at integral
multiples of the integration period are, for the most part,
completely removed. For this reason, the integration
period of the converter is often established to reject
50/60 Hz line noise. The ability to reject such noise is
shown by the plot of Figure 4-1.
In addition to the two phases required for dual slope
measurement (Integrate
and
De-integrate), the
TC530/TC534 performs two additional adjustments to
minimize measurement error due to system offset volt-
ages. The resulting four internal operations (conver-
sion phases) performed each measurement cycle are:
Auto Zero (AZ), Integrator Output Zero (IZ), Input
Integrate (INT) and Reference De-integrate (DINT).
The AZ and IZ phases compensate for system offset
errors and the INT and DINT phases perform the actual
A/D conversion.
FIGURE 4-1:
Integrating Converter
Normal Mode Rejection.
4.2
Auto Zero Phase (AZ)
This phase compensates for errors due to buffer,
integrator and comparator offset voltages. During this
phase,
an
internal
feedback
loop
forces
a
compensating error voltage on auto zero capacitor
(CAZ). The duration of the AZ phase is programmable
via the serial port (see Section 5.1.1 “AZ and INT
Phase Duration”, AZ and INT Phase Duration).
Integrate Voltage = De-integrate Voltage
1
RINTCINT
------------------------ T
INT
0
∫
VIN T
()dT
1
RINTCINT
------------------------ T
DEINT
0
∫
VREF
=
(VIN)
(RINT)(CINT)
[ (TINT) =(V
REF)
]
(RINT)(CINT)
[ (TDEINT) ]
VIN = VREF
[ ]
TINT
TDEINT
Where:
VREF
=
Reference Voltage
TINT
=
Integrate Time
TDEINT
=
Reference Voltage De-integrate
Time
30
20
10
0
0.1/T
1/T
10/T
Input Frequency
Normal
Mode
Rejection
(dB)
T = Measurement
Period
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