TC664/TC665
DS21737A-page 22
2002 Microchip Technology Inc.
7.0
APPLICATIONS INFORMATION
7.1
Connecting to the SMBus
The SMBus is an open collector bus, requiring pull-up
resistors connected to the SDA and SCLK lines. This
FIGURE 7-1:
Pull-up Resistors On
SMBus.
The number of devices connected to the bus is limited
only by the maximum rise and fall times of the SDA and
SCLK lines. Unlike I2C specifications, SMBus does not
specify a maximum bus capacitance value. Rather, the
SMBus specification calls out that the maximum current
through the pull-up resistor be 350 A (minimum,
100 A, is also specified). Therefore, the value of the
pull-up resistors will vary depending on the system’s
bias voltage, VDD. Minimizing bus capacitance is still
very important as it directly effects the rise and fall times
of the SDA and SCLK lines. The range for pull-up resis-
Although SMBus specifications only require the SDA
and SCLK lines to pull down 350 A, with a maximum
voltage drop of 0.4 V, the TC664/TC665 devices have
been designed to meet a maximum voltage drop of
0.4 V with 3 mA of current. This allows lower values of
pull-up resistors to be used, which will allow higher bus
capacitance. If this is to be done, all devices on the bus
must be able to meet the same pull down current
requirements as well.
A possible configuration using multiple devices on the
FIGURE 7-2:
Multiple Devices on SMBus.
7.2
Setting the PWM Frequency
The PWM frequency of the VOUT output is set by the
capacitor value attached to the CF pin. The PWM fre-
quency will be 30 Hz (typical) for a 1 F capacitor. The
relationship between frequency and capacitor value is
linear, making alternate frequency selections easy.
As stated in previous sections, the PWM frequency
should be kept in the range of 15 Hz to 35 Hz. This will
eliminate the possibility of having audible frequencies
when varying the duty cycle of the fan drive.
A very important factor to consider when selecting the
PWM frequency for the TC664/TC665 devices is the
RPM rating of the selected fan and the minimum duty
cycle that you will be operating at. For fans that have a
full speed rating of 3000 RPM or less, it is desirable to
use a lower PWM frequency. A lower PWM frequency
allows for a longer time period to monitor the fan cur-
rent pulses. The goal is to be able to monitor at least
two fan current pulses during the on time of the VOUT
output.
Example: Your system design requirement is to oper-
ate the fan at 50% duty cycle when ambient tempera-
tures are below 20°C. The fan full speed RPM rating is
3000 RPM and has four current pulses per rotation. At
50% duty cycle, the fan will be operating at approxi-
mately 1500 RPM.
EQUATION
If one fan revolution occurs in 40 msec, then each fan
pulse occurs 10 msec apart. In order to detect two fan
current pulses, the on time of the VOUT pulse must be
at least 20 msec. With the duty cycle at 50%, the total
period of one cycle must be at least 40 msec, which
makes the PWM frequency 25 Hz. For this example, a
PWM frequency of 20 Hz is recommended. This would
define a CF capacitor value of 1.5 F.
PI
Cmi
cr
o
SDA
SCLK
VDD
R
M
icr
oc
ont
ro
ller
TC664/TC665
Range for R: 13.2 k
to 46 k for VDD = 5.0 V
SDA SCLK
PIC16F876
Microcontroller
TCN75
Temperature
Sensor
24LC01
EEPROM
TC664/TC665
Fan Speed
Controller
Time for one revolution (msec.)
60 1000
×
1500
------------------------40
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