參數(shù)資料
型號(hào)： TC835C/KW
元件分類(lèi)： ADC
英文描述： 1-CH 4-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQFP44
封裝： 10 X 10 MM, 2 MM HEIGHT, PLASTIC, MQFP-44
文件頁(yè)數(shù)： 23/26頁(yè)
文件大?。?/td> 420K
代理商： TC835C/KW
TC835
DS21478C-page 6
2007 Microchip Technology Inc.
3.0
DETAILED DESCRIPTION
(All Pin Designations Refer to 28-Pin DIP)
3.1
Dual Slope Conversion Principles
The TC835 is a dual slope, integrating analog-to-digital
converter.
An
understanding
of
the
dual
slope
conversion technique will aid in following the detailed
TC835 operational theory.
The conventional dual slope converter measurement
cycle has two distinct phases:
1.
Input signal integration.
2.
Reference voltage integration (de-integration).
The input signal being converted is integrated for a
fixed time period, with time being measured by
counting clock pulses. An opposite polarity constant
reference voltage is then integrated until the integrator
output
voltage
returns
to
zero.
The
reference
integration time is directly proportional to the input
signal.
In a simple dual slope converter, a complete
conversion requires the integrator output to "ramp-up"
and "ramp-down."
A simple mathematical equation relates the input sig-
nal, reference voltage and integration time:
EQUATION 3-1:
For a constant VIN:
EQUATION 3-1:
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as
they are stable during a measurement cycle. An
inherent benefit is noise immunity. Noise spikes are
integrated, or averaged, to zero during the integration
periods. Integrating ADCs are immune to the large
conversion errors that plague successive approxima-
tion converters in high noise environments (see
FIGURE 3-1:
Basic Dual Slope Converter.
3.2
Operational Theory
The TC835 incorporates a system zero phase and
integrator output voltage zero phase to the normal two
phase dual slope measurement cycle. Reduced
system errors, fewer calibration steps and a shorter
overrange recovery time result.
The TC835 measurement cycle contains four phases:
1.
System zero.
2.
Analog input signal integration.
3.
Reference voltage integration.
4.
Integrator output zero.
Internal analog gate status for each phase is shown in
3.2.1
SYSTEM ZERO
During this phase, errors due to buffer, integrator and
comparator offset voltages are compensated for by
charging CAZ (auto zero capacitor) with a compensat-
ing error voltage. With a zero input voltage the
integrator output will remain at zero.
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The
internal input points connect to ANALOG COMMON.
The reference capacitor charges to the reference
voltage potential through SWR. A feedback loop,
closed around the integrator and comparator, charges
the CAZ capacitor with a voltage to compensate for
buffer amplifier, integrator and comparator offset
voltages (see Figure 3-2).
Where:
VREF
=
Reference voltage
TINT
=
Signal integration time (fixed)
TDEINT
=
Reference voltage integration
time (variable)
1
R
INTCINT
------------------------
V
IN T
()DT
0
T
INT
∫
V
REFTDEINT
R
INTCINT
--------------------------------
=
V
IN
V
REFTDEINT
t
INT
--------------------------------
=
+
-
REF
Voltage
Analog Input
Signal
+
-
Display
Switch
Drive
Control
Logic
In
te
grat
or
Ou
tpu
t
Clock
Counter
Polarity Control
Phase
Control
VIN ≈ VREF
Variable
Reference
Integrate
Time
Fixed
Signal
Integrate
Time
Integrator
Comparator
VIN ≈ 1/2 VREF
相關(guān)PDF資料
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TC835C/PI 1-CH 4-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP28
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