參數(shù)資料
型號(hào)： TC835C/KW
元件分類： ADC
英文描述： 1-CH 4-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQFP44
封裝： 10 X 10 MM, 2 MM HEIGHT, PLASTIC, MQFP-44
文件頁數(shù)： 24/26頁
文件大小： 420K
代理商： TC835C/KW
2007 Microchip Technology Inc.
DS21478C-page 7
TC835
FIGURE 3-2:
System Zero Phase.
3.2.2
ANALOG INPUT SIGNAL
INTEGRATION
The TC835 integrates the differential voltage between
the +INPUT and -INPUT pins. The differential voltage
must be within the device Common mode range (-1V
from either supply rail, typically). The input signal polar-
ity is determined at the end of this phase (see
FIGURE 3-3:
Input Signal Integration
Phase.
3.2.3
REFERENCE VOLTAGE
INTEGRATION
The previously charged reference capacitor is con-
nected with the proper polarity to ramp the integrator
output back to zero (see Figure 3-4). The digital read-
ing displayed is:
FIGURE 3-4:
Reference Voltage
Integration Cycle.
3.2.4
INTEGRATOR OUTPUT ZERO
This phase guarantees the integrator output is at 0V
when the system zero phase is entered and that the
true system offset voltages are compensated for. This
phase normally lasts 100 to 200 clock cycles. If an
overrange condition exists, the phase is extended to
6200 clock cycles (see Figure 3-5).
FIGURE 3-5:
Integrator Output Zero
Phase.
TABLE 3-6:
INTERNAL ANALOG GATE STATUS
+
-
+
-
+IN
REF
IN
Analog
Common
IN
SWR
SWIZ SWZ
SWZ
Integrator
Switch Closed
Switch Open
SW
RI
+
Comparator
To
Section
Analog
Input Buffer
RINT
CINT
CREF
CSZ
SW
RI
-
SWI
SWZ
SW
RI
+
SW
RI
-
SWI
SW1
+
-
Digital
+
–
+
–
+IN
REF
IN
Analog
Common
IN
SWR
SWIZ SWZ
SWZ
Integrator
Switch Closed
Switch Open
SW
RI
+
Comparator
To
Section
Analog
Input Buffer
RINT
CINT
CREF
CSZ
SW
RI
-
SWI
SWZ
SW
RI
+
SW
RI
-
SWI
SW1
+
–
Digital
Reading = 10,000
[Differential Input]
VREF
+
–
+
–
+IN
REF
IN
Analog
Common
IN
SWR
SWIZ SWZ
SWZ
Integrator
Switch Closed
Switch Open
SW
RI
+
Comparator
To
Section
Analog
Input Buffer
RINT
CINT
CREF
CSZ
SW
RI
-
SWI
SWZ
SW
RI
+
SW
RI
-
SWI
SW1
+
–
Digital
+
–
+
–
+IN
REF
IN
Analog
Common
IN
SWR
SWIZ SWZ
SWZ
Integrator
Switch Closed
Switch Open
SW
RI
+
Comparator
To
Section
Analog
Input Buffer
RINT
CINT
CREF
CSZ
SW
RI
-
SWI
SWZ
SW
RI
+
SW
RI
-
SWI
SW1
+
–
Digital
Conversion Cycle Phase
SWI
SWRI+SWRI-SWZ
SWR
SW1
SWIZ
Reference Figures
System Zero
—
Closed
—
Input Signal Integration
Closed
—
Reference Voltage Integration
—
Closed*
—
Closed
—
Integrator Output Zero
—
Closed
*Note:
Assumes a positive polarity input signal. SWRI would be closed for a negative input signal.
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