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參數(shù)資料
| 型號(hào)： | TCM320AC54N |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| 中文描述： | 整體式串行接口的PCM編解碼器和過(guò)濾器 |
| 文件頁(yè)數(shù)： | 11/23頁(yè) |
| 文件大?。?/td> | 317K |
| 代理商： | TCM320AC54N |
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TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP
)
SLWS003C – MAY 1992 – REVISED APRIL – 1998
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see
Figure 4)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tpd6
tpd7
tpd8
FSX high to DOUT bit 1 valid
CL = 0 to 10 pF
CL = 0 to 10 pF
30
ns
DCLKX high to DOUT valid, bits 2 to n
40
ns
FSX low to DOUT bit n Hi-Z
20
ns
PARAMETER MEASUREMENT INFORMATION
All timing parameters are referenced to V
IH
and V
IL
. Bit 1 = MSB (most significant bit) and is clocked in first on DIN
or clocked out first on DOUT. Bit n = LSB (least significant bit) and is clocked in last on DIN or is clocked out last on
DOUT. N = 8 for the companded mode, and N = 16 for the linear mode.
N–1
N
1
2
3
4
N–1
N
1
N+1
N
N–1
N–2
4
3
2
1
0
CLK
FSR
DIN
tsu(FSR)
th(FSR)
See Note B
See Note A
th(DIN)
tsu(DIN)
Receive Time Slot
20%
20%
80%
80%
See Note C
NOTES: A. This window is allowed for FSR high.
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.
N–2
Figure 1. Fixed-Data Rate Mode, Receive Side Timing Diagram
N–1
N–2
3
2
1
N+1
N
N–1
N–2
4
3
2
1
0
N
th(FSX)
CLK
FSX
DOUT
TSX
See Note B
tpd2
tpd3
tpd1
tpd4
tpd5
Transmit Time Slot
tsu(FSX)
20%
80%
20%
80%
See Note C
20%
80%
See Note A
NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low (th(FSX) max determined by data collision considerations).
C. Transitions are measured at 50%.
Figure 2. Fixed-Data Rate Mode, Transmit Side Timing Diagram
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