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參數(shù)資料
| 型號： | TDA10085HT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Single chip DVB-S/DSS channel receiver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 93K |
| 代理商： | TDA10085HT |
2001 Aug 31
5
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
TDA10085HT
6
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
XIN
XOUT
1
2
I
I
crystal oscillator input and output pins; in a typical application, a
fundamental oscillator crystal is connected between pins XIN and
XOUT; see note 1
digital core supply voltage (typically 1.8 V)
analog supply voltage for the PLL (typically 3.3 V)
analog ground for the PLL
digital PLL core ground voltage; see note 2
digital PLL core supply voltage (typically 1.8 V)
digital ADC supply voltage (typically 1.8 V)
digital ADC ground voltage; see note 2
analog ADC supply voltage (typically 3.3 V)
analog ground voltage
analog signal input for channel Q; see note 1
negative analog voltage reference output (typically 1.25 V); a
decoupling capacitor (typically 0.1
μ
F) must be placed as close as
possible between VREFN and GND
positive analog voltage reference output (typically 2 V); a decoupling
capacitor (typically 0.1
μ
F) must be placed as closed as possible
between VREFP and GND
analog signal input for channel I; see note 1
analog supply voltage (typically 3.3 V); a 0.1
μ
F decoupling capacitor
must be placed between AVD and AVS
SADDR0 input signal is the LSB of the I
2
C-bus address of the
TDA10085; other bits of the address are set internally to 000111,
therefore the complete I
2
C-bus address is (MSB to LSB):
0, 0, 0, 1, 1, 1 plus the SADDR0 bit; see note 1
test input; must be connected to ground for normal operation; see
note 1
enable serial interface input; when HIGH, the serial transport stream
is present on the boundary scan pins (TRST, TDO, TCK, TDI
and TMS); when LOW, the boundary scan pins are available; note 1
input to select the I
2
C-bus internal system clock frequency (depends
on the crystal frequency); internal I
2
C-bus clock is XIN when
IICDIV = 0 and XIN/4 if IICDIV = 1; see note 1
control line output 1; this pin function is directly programmable
through the I
2
C-bus interface; default value is logic 1; open-drain
output requiring an external pull-up resistor to 3.3 V or to 5 V
control line output 2; this pin function is directly programmable
through the I
2
C-bus interface; default value is logic 1; open-drain
output requiring an external pull-up resistor to 3.3 V or to 5 V
digital ground voltage; see note 2
digital 5 V supply voltage; required for the 5 V tolerance of inputs
digital core ground voltage; see note 2
VDDI
PLLVCC
PLLGND
DGND
DVCC
VDDI
VSSI
VDD3
AVS
VIN2
VREFN
3
4
5
6
7
8
9
10
11
12
13
supply
supply
ground
ground
supply
supply
ground
supply
ground
I
O
VREFP
14
O
VIN1
AVD
15
16
I
supply
SADDR0
17
I
TMD
18
I
ENSERI
19
I
IICDIV
20
I
CTRL1
21
OD
CTRL2
22
OD
VSSE
VDDE5
VSSI
23
24
25
ground
supply
ground
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