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參數(shù)資料
| 型號(hào)： | TDA10085HT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Single chip DVB-S/DSS channel receiver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 93K |
| 代理商： | TDA10085HT |
2001 Aug 31
6
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
TDA10085HT
VDDI
VDDE
SDA_0
26
27
28
supply
supply
I/OD
digital core supply voltage (typically 1.8 V)
digital supply voltage (typically 3.3 V)
I
2
C-bus bidirectional serial input/ open drain output; equivalent to
SDA but with a high-impedance state programmable via the I
2
C-bus;
a pull-up resistor must be connected between this pin and DVCC
I
2
C-bus clock output; equivalent to SCL but with a high-impedance
state programmable via the I
2
C-bus; open drain output requiring an
external pull-up resistor to 5 V
PWM encoded output signal for AGC; the refresh frequency of AGC
information is the sampling frequency divided by 2048, the maximum
signal frequency on the VAGC output is
1
/
4
×
AGC sampling clock;
the VAGC output can be selected by I
2
C-bus to be open-drain or
have 3.3 V capability (typically, output VAGC is fed to the AGC
amplifier through a single RC network)
control line 3 input/open drain output; this pin function is directly
programmable through the I
2
C-bus interface and is an input by
default; it requires a pull-up resistor to 3.3 or 5 V, or a pull-down
resistor to GND
I
2
C-bus bidirectional serial data input/output; the open-drain output
requires a pull-up resistor (typically 2.2 k
) to be connected between
SDA and 5 V for proper operation
I
2
C-bus clock input; nominally a square wave with a maximum
frequency of 400 kHz generated by the system I
2
C-bus master; see
note 1
boundary scan mode: test mode select input/output; provides the
logic levels needed to change the TAP controller from state to state
serial mode enabled (ENSERI = 1): serial TS uncorrectable output;
when not in serial mode, TMS must be set to VSS
boundary scan mode: test clock input/output; TCK is an independant
clock used to drive the TAP controller
serial mode enabled (ENSERI = 1): TCK is the serial TS clock
output; when not in serial mode, TCK must be set to VSS
boundary scan mode: test reset input/output; TRST is an active-LOW
reset input to the TAP controller
serial mode enabled (ENSERI = 1): test reset input/output; TRST is
the serial TS PSYNC output; when not in serial mode, TRST must be
set to VSS
front-end locked output signal that goes HIGH when demodulator,
Viterbi decoder and de-interleaver are all synchronized; open-drain
output requiring an external pull-up resistor to 3.3 or 5 V; can be set
via the I
2
C-bus to be an interrupt pin
digital core supply voltage (typically 1.8 V)
digital core ground voltage; see note 2
boundary scan mode: test data and instruction serial input
serial mode enabled (ENSERI = 1): serial TS data output; must be
set to VSS when not in serial mode
SCL_0
29
OD
VAGC
30
O or OD
CTRL3
31
I/OD
SDA
32
I/OD
SCL
33
I
TMS
34
I/O
TCK
35
I/O
TRST
36
I/O
FEL
37
OD
VDDI
VSSI
TDI
38
39
40
supply
ground
I/O
SYMBOL
PIN
TYPE
DESCRIPTION
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| TDA1011 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2 to 6 W audio power amplifier |
| TDA1011A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2 to 5W audio power amplifier with preamplifier |
| TDA1013B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:4 W audio power amplifier with DC volume control |
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