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參數(shù)資料
| 型號(hào)： | TDA1306T-T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | DUAL, SERIAL INPUT LOADING, 20-BIT DAC, PDSO24 |
| 文件頁(yè)數(shù)： | 7/24頁(yè) |
| 文件大?。?/td> | 166K |
| 代理商： | TDA1306T-T |
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1998 Jan 06
15
Philips Semiconductors
Product specication
Noise shaping lter DAC
TDA1306T
AC CHARACTERISTICS (DIGITAL)
VDDD =VDDA =VDDO 4.5 to 5.5 V; all voltages referenced to ground (pins 2, 9 and 23); Tamb = 40 to +85 °C; unless
otherwise specified.
Notes
1. A clock frequency of up to 96fs is possible in the event of a rising edge of BCK occurring during SYSCLK = LOW.
2. A clock frequency of up to 64fs is possible in the event of a rising edge of BCK occurring during SYSCLK = LOW.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
TWX
clock cycle time
fsys = 384fs; normal speed
54.2
59.1
104
ns
fsys = 192fs; double speed
54.2
59.1
104
ns
fsys = 256fs; normal speed
81.3
88.6
156
ns
fsys = 128fs; double speed
81.3
88.6
156
ns
tCWL
fsys LOW level pulse width
22
ns
tCWH
fsys HIGH level pulse width
22
ns
Serial input data timing (see Fig.8)
fs
word select input audio
sample frequency
normal speed
25
44.1
48
kHz
double speed
50
88.2
96
kHz
fBCK
clock input frequency
(data input rate)
fsys = 384fs; normal speed; note 1
64fs
kHz
fsys = 192fs; double speed; note 1
64fs
kHz
fsys = 256fs; normal speed
64fs
kHz
fsys = 128fs; double speed; note 2
48fs
kHz
tr
rise time
20
ns
tf
fall time
20
ns
tH
bit clock HIGH time
55
ns
tL
bit clock LOW time
55
ns
tsu
data set-up time
20
ns
th
data hold time
10
ns
tsuWS
word select set-up time
20
ns
thWS
word select hold time
10
ns
Microcontroller interface timing (see Fig.9)
tL
input LOW time
2
s
tH
Input HIGH time
2
s
tsuDC
set-up time DATA to CLOCK
1
s
thCD
hold time CLOCK to DATA
1
s
tsuCR
set-up time CLOCK to RAB
1
s
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