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參數(shù)資料
| 型號： | TDA1388T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | CAP .012UF 200V B SERIES POLY |
| 中文描述： | SERIAL INPUT LOADING, 20-BIT DAC, PDSO28 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大小： | 168K |
| 代理商： | TDA1388T |
1995 Dec 08
7
Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC
for CD-ROM audio applications
TDA1388T
S
TATIC
-
PIN MODE
In the static-pin mode most of the features have a default
value (see Table 3). The features that are controlled by the
external pins are, mute left channel, mute right channel
and de-emphasis.
Table 4
External pin feature control in the static-pin
mode
M
ICROCONTROLLER MODE
The exchange of data and control information between the
microcontroller and the TDA1388T is accomplished
through a serial hardware interface comprising the
following pins;
APPL0: microcontroller interface data line.
APPL1: microcontroller interface mode line.
APPL2: microcontroller interface clock line.
Information transfer through the microcontroller bus is
organized in accordance with the so-called ‘L3’ format, in
which two different modes of operation can be
distinguished; address mode and data transfer mode (see
Figs 4 and 5).
The address mode is required to select a device
communicating via the L3-bus and to define the
destination registers for the data transfer mode. Data
transfer for the TDA1388T can only be in one direction,
input to the TDA1388T to program its sound processing
and other functional features.
Address mode
The address mode is used to select a device for
subsequent data transfer and to define the destination
registers. The address mode is characterized by APPL1
being LOW and a burst of 8 pulses on APPL2,
accompanied by 8 data bits. The fundamental timing is
shown in Fig.4. Data bits 0 to 1 indicate the type of the
subsequent data transfer as shown in Table 5.
PIN
FEATURE
APPL0
APPL1
APPL2
mute left channel
mute right channel
de-emphasis
Table 5
Selection of data transfer
Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
TDA1388T is 000101 (bit 7 to bit 2). In the event that the
TDA1388T receives a different address, it will deselect its
microcontroller interface logic.
Data transfer mode
The selection preformed in the address mode remains
active during subsequent data transfers, until the
TDA1388T receives a new address command. The
fundamental timing of data transfers is essentially the
same as in the address mode, shown in Fig.4. The
maximum input clock and data rate is 64f
s
. All transfers are
bitwise, i.e. they are based on groups of 8 bits. Data will be
stored in the TDA1388T after the eighth bit of a byte has
been received. A multibyte transfer is illustrated in Fig.6.
Programming the sound processing and other features
The sound processing and other feature values are stored
in independent registers. The first selection of the registers
is achieved by the choice of data type that is transferred.
This is performed in the address mode, BIT 1 and BIT 0
(see Table 5). The second selection is performed by the
2 MSBs of the data byte (BIT 7 and BIT 6). The other bits
in the data byte (BIT 5 to BIT 0) is the value that is placed
in the selected registers.
When the data transfer of type “data” is selected, the
features VOLUME_R, VOLUME_L, BASS BOOST and
TREBLE can be controlled. When the data transfer of type
“status” is selected, the features MODE, DE-EMPHASIS,
CHANNEL_MANIP_R and CHANNEL_MANIP_L can be
controlled.
BIT 1
BIT 0
TRANSFER
0
0
data (volume left, volume right, bass
boost and treble)
not used
status (de-emphasis, mode and
channel-manipulation)
not used
0
1
1
0
1
1
Table 6
Data transfer of type “status”
BIT 7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REGISTER SELECTED
0
M1
M0
DE
OR1
OR0
OL1
OL0
MODE (1 : 0), DEEMPHASIS, CHANNEL_MA-
NIP_R (1 : 0), CHANNEL_MANIP_L (1 : 0)
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