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參數(shù)資料
| 型號： | TDA4691T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 信號分離 |
| 英文描述： | Sync Processor with Clock SPC |
| 中文描述： | SYNC SEPARATOR IC, PDSO20 |
| 封裝： | PLASTIC, SOT-163-1, SO-20 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 206K |
| 代理商： | TDA4691T |
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September 1993
9
Philips Semiconductors
Preliminary specification
Sync Processor with Clock (SPC)
TDA4691
f
0
/
V
16
VCO sensitivity
4% control range;
depending on current
at pin 18
360
kHz/V
Input of external oscillator
(pin 15)
V
15
V
15
R
int
C
int
pin voltage AC
pin voltage DC
internal resistance
internal capacitance
see Fig.4(b)
dependent on V
19
see Fig.4(b)
see Fig.4(b)
1
5
7
4
3
V
V
k
pF
13.5 MHz buffer
(pin 13)
V
13
clock HIGH level output voltage
I
13
=
1 mA;
V
12
= 4.5 V
I
13
= 0 mA
I
13
= 2 mA;
V
12
= 5.5 V
see Fig.5
see Fig.5
V
13
= 1.5 V
2.7
V
12
V
V
13
V
13
clock HIGH level output voltage
clock LOW level output voltage
2.7
0
V
12
0.8
V
V
t
r
t
f
D
13
C
L
T
13
rise time
fall time
mark-to-space ratio
load capacitance
jitter on clock output
(peak-to-peak value)
45/55
20
20
55/45
40
2
ns
ns
%
pF
ns
normal time constant
T
2;
measured between
lines 25 and 305
H-output buffer
(pin 11)
V
11
H HIGH level output voltage
I
11
=
1 mA;
V
12
= 4.5 V
I
11
= 0 mA
I
11
= 2 mA;
V
12
= 5.5 V
see Fig.6
see Fig.6
see Fig.6
see Fig.6
see Fig.6
see Fig.6
2.7
V
12
V
V
11
V
11
H HIGH level output voltage
H LOW level output voltage
2.7
0
V
12
0.8
V
V
t
r
t
f
t
3
t
4
t
5
C
L
rise time
fall time
time relation pin 13 to 11
time relation pin 13 to 11
H-pulse width
load capacitance
3
3.0
25
25
25
3.6
55
4.2
40
ns
ns
ns
ns
μ
s
pF
Start of H-pulse
(pin 14)
I
14
t
61
t
62
t
63
t
64
V
14
(t
61
)
current pin 14
time delay pulse between pin 20 and 11
time delay pulse between pin 20 and 11
time delay pulse between pin 20 and 11
time delay pulse between pin 20 and 11
voltage pin 14 (proportional to V
19
)
1.1
0.6
3.8
5.0
0
1.3
0.8
4.0
5.2
±
100
1.5
1.0
4.2
5.4
1
μ
A
μ
s
μ
s
μ
s
μ
s
V
see Fig.6
see Fig.6
see Fig.6
see Fig.6
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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