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參數(shù)資料
| 型號： | TDA4886A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | 140 MHz video controller with I2C-bus |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP24 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-24 |
| 文件頁數(shù)： | 11/52頁 |
| 文件大?。?/td> | 495K |
| 代理商： | TDA4886A |
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1998 Dec 04
11
Philips Semiconductors
Product specification
140 MHz video controller with I
2
C-bus
TDA4886A
10 CHARACTERISTICS
All voltages and currents are measured in a dedicated test circuit which is optimized for best high frequency
performance; all voltages are measured with respect to GND (pins 9 and 14); V
P
= V
P1, 2, 3
= 8 V (pins 7, 21,
18 and 15); T
amb
= 25
°
C; nominal input signals [0.7 V (p-p) at pins 6, 8 and 10]; nominal colour signals at signal
outputs (pins 22, 19 and 16); reference black level (V
rbl
) approximately 0.77 V; nominal settings for brightness and
contrast; maximum settings for OSD contrast and gain; no subcontrast, modulation of contrast or limiting (V
24
≥
5 V);
no OSD fast blanking (pin 1 connected to ground); notes 1 to 3; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
P
I
P
V
P1,2,3
supply voltage (pin 7)
supply current (pin 7)
channel supply voltage
(pins 21, 18 and 15)
channel supply current
(pins 21, 18 and 15)
7.6
7.6
8.0
21
8.0
8.8
25
8.8
V
mA
V
note 4
I
P1,2,3
signal outputs (pins 22,
19 and 16) open-circuit;
V
rbl
≈
0.77 V; notes 4 and 5
signal outputs switched to
switch-off voltage
21
25
mA
V
PSO
supply voltage for signal switch
off (threshold at pin 7)
7.2
V
Input clamping and vertical blanking input, validation of buffered I
2
C-bus data (pin 5)
V
5
input clamping and vertical
blanking input signal
notes 6 and 7
no vertical blanking,
no input clamping
vertical blanking,
no input clamping
input clamping,
no vertical blanking
V
5
= 1 V
pin 5 connected to ground;
note 8
V
5
=
0.1 V; note 8
note 6; see Fig.7
0.1
+1.2
V
1.6
2.6
V
3.5
V
P
V
I
5
input current
80
0.2
60
30
μ
A
μ
A
250
200
100
75
μ
A
ns/V
t
r/f5
rise/fall time for input clamping
pulse, disable for vertical
blanking
width of input clamping pulse
width of vertical blanking pulse
for validation of buffered
I
2
C-bus data
delay between leading edge of
vertical blanking pulse and
validation of buffered I
2
C-bus
data
dead time of I
2
C-bus receiver
after synchronizing vertical
blanking pulse in case of a
completed I
2
C-bus transmission
in buffered mode
t
W5
t
W5I2C
0.6
10
μ
s
μ
s
leading and trailing edge
threshold V
5
= 1.4 V; note 7
t
I2Cvalid
I
2
C-bus transmission in
buffered mode completed;
leading edge threshold
V
5
= 1.4 V; note 7
leading edge threshold
V
5
= 1.4 V; note 7
2
μ
s
t
I2Cdead
15
μ
s
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