參數(shù)資料
型號: TDA7340G
廠商: 意法半導(dǎo)體
英文描述: AUDIO SIGNAL PROCESSOR
中文描述: 音頻信號處理器
文件頁數(shù): 19/27頁
文件大?。?/td> 205K
代理商: TDA7340G
VPEAK
(V)
D95AU332A
20
DEVIATION(KHz)
0.9
1.3
2.3
3.2
DETECTOR OFF (11)
32.5
45
75
OVM=10
OVM=01
OVM=00
Figure 7:
Behaviourof the DeviationDependentThreshold Adiust (Over DeviationDetector)
2.2V(00)
1.8V(01)
1.2V(10)
TRIG. THRESHOLD
0.9V
VPEAK
E’
D95AU333A
MONO
STEREO
noisy signal
good signal
ATC_SB OFF (11)
NOISE
3V
Figure 6:
Behaviourof the Field StrengthControlled Threshold Adjustment
MUTE & PAUSEFEATURES
The TDA7340G provides three types of mute,
controlled via I2C bus (see pag.12, MUTE BYTE
register).
SOFT MUTE
Bit
D0=1
SoftMute ON
Bit
D0=0
Soft Mute OFF
It allows an automatic soft muting and unmuting
of the signal.
The time constant is fixed by an external capaci-
tor Csm inserted between pin Csm and ground.
Once fixed the external capacitor, two different
slopes (time constant) are selectable by program-
mationof bitD1.
Bit
D1=1
fast slope (I=Imax)
Bit
D1=0
slow slope (I=Imin)
The soft mute generates a gradual signal de-
creasing avoiding big click noise of an immediate
high attenuation, without necessity to program a
sequence of decreasing volume levels. A re-
sponse example is reported in Fig.12 (mute) and
Fig.13 (unmute). The final attenuation obtained
with soft muteON is 60dB typical.
The used reference parameter is the delay time
taken to reach 20dB attenuation (no matter what
the signal level is).
Usinga capacitorCsm=22nF this delay is:
d= 1.8mswhenselectedFastslopemode(bitD1=1)
d= 25ms whenselectedSlowslopemode(bitD1=0)
TDA7340G
19/27
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