參數(shù)資料
型號(hào)： TDA9109S
廠(chǎng)商： 意法半導(dǎo)體
英文描述： LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
中文描述： 低費(fèi)用偏轉(zhuǎn)處理器多同步監(jiān)測(cè)儀
文件頁(yè)數(shù)： 17/30頁(yè)
文件大?。?/td> 266K
代理商： TDA9109S
I.6 - Sync IdentificationStatus
The MCU can read (address read mode : 8D) the
statusregistervia the I
2
C bus, and then select the
sync priority dependingon thisstatus.
Among other data this register indicatesthe pres-
ence of sync pulses on H/HVIN, VSYNCIN and
(when 12V is supplied) whether a Vext has been
extractedfromH/HVIN.Bothhorizontalandvertical
sync are detectedeven if only5V is supplied.
In order to choose the right sync priority the MCU
may proceed as follows (see I
2
C AddressTable):
- refresh the statusregister,
- wait at least for 20ms(Max. vertical period),
- read this status register.
Sync priority choice shouldbe :
Sync priority
Subaddress
03 (D8)
No
Yes Yes
1
Yes
Yes
No
0
Vext
det
H/V
det
V
det
Comment
Sync type
Separated H & V
Composite TTL H&V
Ofcourse,whenthechoiceismade,wecanrefresh
the sync detections and verify that the extracted
Vsyncis presentand thatno synctypechangehas
occured. The sync processor also gives sync po-
larity information.
I.7 - IC status
TheICcaninformtheMCUaboutthe 1sthorizontal
PLLand vertical sectionstatus (lockedor not) and
about the XRAYprotection (activated or not).
Resetting the XRAY internal latch can be done
either by decreasing the V
CC
or V
DD
supply or
directlyresetting it via the I
2
C interface.
I.8 - Sync Inputs
BothH/HVIN andVSYNCINinputsareTTLcom-
patible triggers with hysterisis to avoid erratic
detection. Both inputs include a pull up resistor
connected to V
DD
.
I.9 - Sync ProcessorOutput
The sync processor indicates on the HLOCKOUT
Pin whether 1st PLL is locked to an incoming
horizontal sync. HLOCKOUT is a TTL compatible
CMOS output. Its level goes to high when locked.
In the sametime the D8 bit of the statusregister is
setto 0.
This information is mainly used to trigger safety
procedures (like reducing B+ value) as soon as a
changeis detectedon the incoming sync.
II - HORIZONTAL PART
II.1 - Internal Input Conditions
A digital signal (horizontal sync pulse or TTL
composite) is sent by the sync processor to the
OPERATINGDESCRIPTION
(continued)
9
Figure 5
d
d
C
TRAMEXT
9
Figure 6
horizontalinput.Itmaybepositiveornegative(see
Figure5).
Using internal integration, both signals are recog-
nized if Z/T < 25%. Synchronizationoccurs on the
leadingedge of the internal sync signal. The mini-
mum value of Z is 0.7
μ
s.
Another integration is able to extract the vertical
pulsefromcompositesyncifthedutycycleishigher
than25% (typically d = 35%)(see Figure 6).
Thelastfeatureperformedis theremovalof equali-
zationpulsesto avoidparasiticpulsesonthephase
comparator(which would be disturbed by missing
or extraneouspulses).
II.2 - PLL1
The PLL1 consists of a phase comparator, an
external filter and a voltage-controlled oscilla-
tor (VCO).
Thephasecomparatoris a”phasefrequency”type
designed in CMOStechnology.This kind of phase
detectoravoids lockingon wrong frequencies.It is
followed by a ”charge pump”, composed of two
current sources : sunk and sourced (typi-
cally I = 1mA when locked and I = 140
μ
A when
unlocked).This differencebetween lock/unlock al-
lows smooth catching of the horizontal frequency
by PLL1. This effect is reinforced by an internal
original slow down system when PLL1 is locked,
avoiding the horizontal frequency changing too
quickly.
The dynamic behaviour of PLL1 is fixed by an
external filter which integrates the current of the
charge pump. A ”CRC” filter is generally used
(seeFigure 7).
TDA9109/SN
17/30
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