參數(shù)資料
型號(hào)： TDA9109S
廠商： 意法半導(dǎo)體
英文描述： LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
中文描述： 低費(fèi)用偏轉(zhuǎn)處理器多同步監(jiān)測(cè)儀
文件頁(yè)數(shù)： 19/30頁(yè)
文件大?。?/td> 266K
代理商： TDA9109S
OPERATINGDESCRIPTION
(continued)
Thesyncfrequencymustalwaysbehigherthanthe
free running frequency.For example, when using
a sync range between 24kHz and 100kHz, the
suggestedfree runningfrequency is 23kHz.
Thiscanbeobtainedonlybyadjustingf0(forinstance,
makingR0adjustable).If no adjustmentis possible,
more margin must be provided to cope with the
componentsspread :
±
8% for the IC,
±
1% for R
0
,
±
2 or5% forC
0
,leadingto
±
11%or 14%on f0.The
same percentage of frequency range will lost at
upper end of the range.
Another feature is the capability for the MCU to
force the horizontal frequencythrough I
2
C to 2xf0
or 3xf0 (for burn-in mode or safety requirements).
Inthiscase,theinhibitionswitchisopened,leaving
PLL1 free, but the voltage on PLL1 filter is forced
to 2.66V (for 2xf0) or 4.0V (for 3xf0).
PLL1ensuresthecoincidencebetweentheleading
edge of the sync signal and a phase reference
obtained by comparison between the sawtooth of
the VCO and an internal DC voltage which is I
2
C
adjustablebetween 2.8Vand 4.0V(corresponding
to
±
10%)(seeFigure 10).
H Osc
Sawtooth
H Drive
1.6V
4.0V
6.4V
7/8T
H
1/8T
H
Ts
Duty Cycle
Internally
Shaped Flyback
Flyback
9
The duty cycle of H-drive is fixed (48%).
Figure 11:
PLL2Timing Diagram
H Osc
Sawtooth
Phase REF1
H Synchro
1.6V
Vb
6.4V
2.8V < Vb < 4.0V
7/8T
H
1/8T
H
Phase REF1is obtainedbycomparisonbetweenthesawtoothand
a DC voltage adjustable between 2.8V and 4.0V. The PLL1 en-
sures the exact coincidence between the signal phase REF and
HSYNC. A
±
T
H
/10 phase adjustment is possible.
9
Figure 10 :
PLL1 TimingDiagram
The TDA9109/SN also includes a Lock/Unlock
identification block which senses in real time
whether PLL1 is locked or not on the incoming
horizontalsyncsignal. The resultinginformation is
available on HLOCKOUT(see Sync Processor).
When PLL1 is unlocked, it forces HLOCKOUT to
high level.
The lock/unlock information is also available
throughthe I
2
C read.
II.3 - PLL2
PLL2 ensures a constant position of the shaped
flyback signal in comparison with the sawtooth of
theVCO, takinginto accountthe saturationtimeTs
(seeFigure 11).
The phase comparator of PLL2 (phase type com-
parator) is followed by a charge pump (typical
outputcurrent: 0.5mA).
The flyback input consists of an NPN transistor.
This input must be current driven. The maximum
recommended input current is 5mA (see Fig-
ure 12).
The duty cycle is fixed (48%).
The maximum storage time (Ts Max.) is (0.44T
H
-
T
FLY
/2). Typically, T
FLY
/T
H
is around 20% which
means that Ts max is around 34% of T
H
.
TDA9109/SN
19/30
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