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參數(shù)資料
| 型號： | TDA9332H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | I2C-bus controlled TV display processors |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 32/56頁 |
| 文件大?。?/td> | 228K |
| 代理商： | TDA9332H |
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2000 May 08
32
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV display processors
TDA933xH series
When the supply voltage suddenly decreases, pin FBCSO (fixed beam current switch-off) of the TDA933xH must be
pulled high. In this situation, the procedure is as follows:
a) Vertical scan is completed.
b) Vertical flyback is completed.
c) The fixed beam current is forced via the black current loop (if FBC = 1). The horizontal output keeps running.
As the supply voltage for the line transformer decreases, the EHT voltage will also decrease.
d) If OSO = 1, the vertical deflection stays in overscan position; if OSO = 0, the vertical deflection keeps running.
e) When the supply voltage of the TDA933xH drops below the POR level, horizontal output and fixed beam current
are stopped.
26. The discharge current for the picture tube can be increased with an external current division circuit on the black
current input (pin 44). The current division should only be active for high cathode currents, so that the operation of
the black current stabilization loop is not affected. When the feedback current supplied to pin 44 is less than 1mA,
the DC level at the RGB outputs will go to the maximum value of 6.0 V (2-point black current stabilization) or 5.6 V
(1-point or no black current stabilization).
27. A stable switching of the H
D
input is realized by using a Schmitt trigger input.
28. The simplified circuit diagram of the oscillator is given in Fig.3. To ensure that the oscillator will start-up, the ceramic
resonator must fulfil the following condition:
Example: When the resonator is loaded with 60 pF (this is a typical value for a 12 MHz resonator), the series
resistance of the resonator must be smaller than 30
.
A suitable ceramic resonator for use with the TDA933xH is the Murata CST12.0MT, which has built-in load
capacitances C
a
and C
b
. For higher accuracy, it is also possible to use a quartz crystal, which is even less critical
with respect to start-up because of its lower load capacitance.
29. Pin HSEL must be connected to ground in a 1f
H
application; it must be left open circuit for a 2f
H
application. The
TDA9331H and TDA9332H can be switched to a multi-sync mode, in which the horizontal frequency can vary
between 15 and 25 kHz (1f
H
mode) or 30 and 50 kHz (2f
H
mode).
30. The indicated tolerance on the free-running frequency is only valid when an accurate reference frequency (obtained
with an accurate 12 MHz crystal) is used. The tolerance of the reference resonator must be added to obtain the real
tolerance on the free-running frequency.
31. The correction factor k of the phase-2 loop is defined as the amount of correction per line period of a phase error
between the horizontal flyback pulse and the internal phase-2 reference pulse. When k = 0.5, the phase error
between the flyback pulse and the internal reference is halved each line period.
32. The control range of the second control loop depends on the line frequency. The maximum control range from the
rising edge of HOUT to the centre of the flyback pulse is always 37% of one line period, for the centre position of the
dynamic phase compensation (4.0 V at pin 14).
33. The dynamic phase compensation input (pin 14) is connected to an internal reference voltage of 4.0 V via a resistor
of 100 k
. If dynamic phase compensation is not used, this pin should be decoupled to ground (pin 19) via a
capacitor of 100 nF.
34. The range of parallelogram and bow correction is proportional to the width of the horizontal flyback pulse. For zero
correction, use DAC setting 7 DEC or 0111 (bin). The effect of the corrections is shown in Fig.16.
35. For safe operation of the horizontal output transistor and to obtain a controlled switch-on time of the EHT, the
horizontal drive starts up in a slow start mode. The horizontal drive starts with a very short ‘on-time’ of the horizontal
output transistor (line locked clock pulse, i.e. 72 ns), the ‘off-time’ of the transistor is identical to the ‘off-time’ in normal
operation. The starting frequency during switch-on is therefore approximately twice the normal value. The t
on
is
slowly increased to the nominal value in approximately 160 ms (see Fig.15). When the nominal frequency is reached,
the PLL is closed such that only very small phase corrections are necessary. This ensures safe operation of the
output stage.
.
C
L
2
R
i
1.1
≤
×
10
19
–
×
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