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參數(shù)資料
| 型號： | TDA9332H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | I2C-bus controlled TV display processors |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 39/56頁 |
| 文件大?。?/td> | 228K |
| 代理商： | TDA9332H |
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2000 May 08
39
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV display processors
TDA933xH series
handbook, full pagewidth
MGS897
0.75
μ
s
2.35
μ
s
2.40
μ
s
5.5
μ
s
mid blank = mid flyback
37 LLC = 2.67
μ
s
22 LLC = 1.59
μ
s
HD input
HSHIFT
2fH NTSC
signal
(fH = 31.47 kHz)
CLP pulse
counter
blanking
0.606
μ
s
0.592
μ
s
1.993
μ
s
3.784
μ
s
50 ns
mid blank = mid flyback
18 LLC = 1.22
μ
s
HD input
HDTV
signal
(fH = 33.75 kHz)
CLP pulse
0.592
μ
s
15 LLC = 1.01
μ
s
counter
blanking
(a) Timing in 2fH TV mode (HDTV = 0, HDCL = 0)
(b) Timing in HDTV mode (HDTV = 1, HDCL = 1)
HSHIFT
40 LLC = 2.69
μ
s
+
14 LLC
16 LLC
40 LLC = 2.89
μ
s
+
14 LLC
16 LLC
Fig.11 Timing of clamp pulse and line blanking in 2f
H
TV mode and HDTV mode.
Video signals are shown as illustration only. All horizontal timing signals in the IC are solely related to the start of the H
D
pulse
that is applied to the IC.
All horizontal timing signals are generated with the help of the internal line locked clock (LLC). One line period is always divided
into 440 line locked clock pulses. Time periods depicted in the figure are only valid for line frequencies mentioned.
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