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參數(shù)資料
| 型號： | TDA9851T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | I2C-bus controlled economic BTSC stereo decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO24 |
| 封裝： | 7.5 MM, PLASTIC, SO-24 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 145K |
| 代理商： | TDA9851T |
1997 Nov 12
6
Philips Semiconductors
Product specification
I
2
C-bus controlled economic BTSC stereo
decoder
TDA9851
FUNCTIONAL DESCRIPTION
Stereo decoder
The composite signal is fed into a pilot detector/pilot
cancellation circuit and into the MPX demodulator.
The main L + R signal passes a 75
μ
s fixed de-emphasis
filter and is fed into the dematrix circuit. The decoded
sub-signal L
R is sent to the VCA circuit. To generate the
pilot signal the stereo demodulator uses a PLL circuit
including a ceramic resonator.
Mode selection
The L
R signal is fed via the internal VCA circuit to the
dematrix/switching circuit. Mode selection is achieved via
the I
2
C-bus.
Automatic volume level control
The automatic volume level stage controls its output
voltage to a constant level of typically 200 mV (RMS) from
an input voltage range between 0.1 to 1.1 V (RMS).
The circuit adjusts variations in modulation during
broadcasting and because of changes in the programme
material. The function can be switched off. To avoid
audible plops during the permanent operation of the AVL
circuit a soft blending scheme has been applied between
the different gain stages. A capacitor (4.7
μ
F) at pin C
AV
determines the attack and decay time constants.
In addition the ratio of attack and decay times can be
changed via the I
2
C-bus.
Integrated filters
The filter functions necessary for stereo demodulation are
provided on-chip using transconductor circuits. The filter
frequencies are controlled by the filter reference circuit via
the external resistor R4.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1.
Machine model class B.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
V
SDA
, V
SCL
supply voltage
voltage of SDA and SCL to GND
0
0
0
0
20
65
9.9
V
CC
9
V
CC
+70
+150
V
V
V
V
°
C
°
C
V
V
CC
< 9 V
V
CC
≥
9 V
V
n
T
amb
T
stg
V
es
voltage of all other pins to GND
operating ambient temperature
storage temperature
electrostatic handling
T
j
< 125
°
C
note 1
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
R
th(j-a)
thermal resistance from junction to ambient
TDA9851 (SOT234-1; SDIP24)
TDA9851T (SOT137-1; SO24)
in free air
55
90
K/W
K/W
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