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參數(shù)資料
| 型號(hào)： | TDA9870A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Digital TV Sound Processor DTVSP |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP64 |
| 封裝： | SHRINK, PLASTIC, DIP |
| 文件頁(yè)數(shù)： | 64/88頁(yè) |
| 文件大?。?/td> | 362K |
| 代理商： | TDA9870A |
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1998 Aug 10
64
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
10.3.31 F
EATURE INTERFACE CONFIGURATION REGISTER
10.3.31.1 Definition
Table 71
Subaddress 36 (note 1)
Notes
1.
2.
3.
4.
5.
The default setting at power-up is 00000000.
System clock frequency select; see Table 72.
System clock output on/off; see Table 73.
Serial output format; see Table 73.
I
2
S-bus outputs on/off; see Table 73.
Table 72
System clock frequency select
Note
1.
With 16.384 MHz, the duty cycle is 33% : 67%.
Table 73
Description of Table 71
MSB
LSB
B7
0
B6
0
B5
0
B4
B3
B2
B1
B0
SYSCL1
(2)
SYSCL0
(2)
SYSOUT
(3)
I
2
SFORM
(4)
I
2
SOUT
(5)
B4
B3
SYSCLK OUTPUT
FREQUENCY (MHz)
0
0
1
1
0
1
0
1
256f
s
384f
s
512f
s
768f
s
8.192
12.288
16.384; note 1
24.576
NAME
I
2
SOUT
HIGH/LOW
FUNCTION
HIGH
Enables the output of serial audio data (2 pins) plus serial bit clock and word select in a
format determined by the I
2
SFORM bit. The TDA9870A is then an I
2
S-bus master.
the outputs mentioned will be 3-stated, thereby improving the EMC performance
an MSB-aligned, MSB-first output format is selected, i.e. a level change at the word
select pin indicates the beginning of a new audio sample
the standard I
2
S-bus output format is selected
enables the output of a system (or master) clock signal at pin SYSCLK
the output will be off, thereby improving the EMC performance
LOW
HIGH
I
2
SFORM
LOW
HIGH
LOW
SYSOUT
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| TDA9873HS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multistandard dual carrier stereo sound decoder |
| TDA9874A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital TV sound demodulator/decoder |
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