參數(shù)資料
型號(hào)： TE28F020-120
廠商： INTEL CORP
元件分類： DRAM
英文描述： 28F020 2048K (256K X 8) CMOS FLASH MEMORY
中文描述： 256K X 8 FLASH 12V PROM, 120 ns, PDSO32
封裝： 0.310 X 0.720 INCH, TSOP-32
文件頁(yè)數(shù)： 9/38頁(yè)
文件大?。?/td> 878K
代理商： TE28F020-120
E
28F020
9
Table 2. 28F020 Bus Operations
Mode
V
PP(1)
A
0
A
9
CE#
OE#
WE#
DQ
0
–DQ
7
Read
V
PPL
A
0
A
9
V
IL
V
IL
V
IH
Data Out
Output Disable
V
PPL
X
X
V
IL
V
IH
V
IH
Tri-State
READ-
Standby
V
PPL
X
X
V
IH
X
X
Tri-State
ONLY
Intelligent Identifier
(Mfr)
(2)
V
PPL
V
IL
V
ID(3)
V
IL
V
IL
V
IH
Data = 89H
Intelligent Identifier
(Device)
(2)
V
PPL
V
IH
V
ID(3)
V
IL
V
IL
V
IH
Data = BDH
Read
V
PPH
A
0
A
9
V
IL
V
IL
V
IH
Data Out
(4)
READ/
Output Disable
V
PPH
X
X
V
IL
V
IH
V
IH
Tri-State
WRITE
Standby
(5)
V
PPH
X
X
V
IH
X
X
Tri-State
Write
V
PPH
A
0
A
9
V
IL
V
IH
V
IL
Data In
(6)
NOTES:
1.
2.
Refer to DC Characteristics When V
PP
= V
PPL
memory contents can be read but not written or erased.
Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. Al other
addresses low.
V
ID
is the intelligent identifier high voltage. Refer to DC Characteristics
Read operations with V
PP
= V
PPH
may access array data or the intelligent identifier codes.
With V
PP
at high voltage, the standby current equals I
CC
+ I
PP
(standby).
Refer to Table 3 for valid data-in during a write operation.
X can be V
IL
or V
IH
.
3.
4.
5.
6.
7.
2.2
Write Protection
The command register is only active when V
PP
is
at high voltage. Depending upon the application,
the system designer may choose to make the V
PP
power supply switchable
—available only when
memory updates are desired. When V
PP
= V
PPL
,
the contents of the register default to the Read
command, making the 28F020 a read only
memory. In this mode, the memory contents
cannot be altered.
Or, the system designer may choose to “hardwire”
V
PP
, making the high voltage supply constantly
available. In this case, all command register
functions are inhibited whenever V
CC
is below the
write lockout voltage V
LKO
(see
Power-Up/Down
Protection
).
The
28F020
accommodate either design practice, and to
encourage optimization of the processor memory
interface.
is
designed
to
The two step program/erase write sequence to the
command register provides additional software
write protection.
2.2.1
BUS OPERATIONS
2.2.1.1
Read
The 28F020 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE#) is the power control
and should be used for device selection. Output
Enable (OE#) is the output control and should be
used to gate data from the output pins,
independent of device selection. Refer to AC read
timing waveforms.
When V
PP
is high (V
PPH
), the read operation can
be used to access array data, to output the
intelligent identifier codes, and to access data for
program/erase verification. When V
PP
is low (V
PPL
),
the read operation can
only
access the array data.
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