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| 型號(hào)： | TH50VSF3582AASB |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS |
| 中文描述： | 東芝多芯片集成電路硅柵CMOS |
| 文件頁(yè)數(shù)： | 43/50頁(yè) |
| 文件大?。?/td> | 548K |
| 代理商： | TH50VSF3582AASB |
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TH50VSF3582/3583AASB
2001-06-08 43/50
TIMING FOR SWITCHING BETWEEN FLASH AND SRAM MODES
Notes:
(1)
WE remains High during a Read cycle.
(2)
If
remain High-Impedance.
S
1
CE
goes Low (or CE2S goes High) at the same time as or after WE goes Low, the outputs will
(3)
If
remain High-Impedance.
S
1
CE
goes High (or CE2S goes Low) at the same time as or before WE goes High, the outputs will
(4)
If OE is High during a Write cycle, the outputs will remain High-Impedance.
(5)
Because I/O pins may be in Output state at this point, input signals of the opposite value must not be
applied.
(6)
D
OUT
6 stops toggling when the last command has been completed.
CEF
CE2S
t
CCR
t
CCR
S
1
CE
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