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參數(shù)資料
| 型號： | TH58NVG1S3AFT05 |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| 中文描述： | 東芝馬鞍山數(shù)字集成電路硅柵CMOS |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 368K |
| 代理商： | TH58NVG1S3AFT05 |
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2003-05-19A
15/32
TH58NVG1S3AFT05
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information. The device
pin-outs are configured as shown in Figure 1.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the
operation mode command into the internal command register.
The command is latched into the command register from the
I/O port on the rising edge of the
WE
signal while CLE is
High.
Address Latch Enable: ALE
The ALE signal is used to control loading of either address
information or input data into the internal address/data
register.
Address information is latched on the rising edge of
WE
if
ALE is High.
Input data is latched if ALE is Low.
Chip Enable:
The device goes into a low-power Standby mode when
CE
goes High during the device is in Ready state. The
CE
signal is ignored when device is in Busy state (
RY
operation, and will not enter Standby mode even if the
CE
input goes High.
BY
/
L ), such as during a Program or Erase or Read
Write Enable:
The
WE
signal is used to control the acquisition of data from the I/O port.
Read Enable:
The
RE
signal controls serial data output. Data is available t
REA
after the falling edge of
RE
.
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.
Write Protect:
The
WP
signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when
WP
is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
The
BY
/
RY
output signal is used to indicate the operating condition of the device. The
BY
/
RY
= L) during the Program, Erase and Read operations and will return to Ready state
= H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with appropriate resister..
BY
/
RY
signal is
in Busy state (
(
BY
/
RY
RE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
NC
V
CC
V
SS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
BY
/
RY
NC
V
CC
V
SS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
RE
NC
Figure 1. Pinout
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